Abstract: A built-in self-test scheme is presented for a carry save array multiplier in which an accumulator is designed as a test pattern generator and a response compactor. A modified deterministic test sequence is deduced. Analysis and Experiment results show that all the non-redundant stuck-at faults can be covered. As in current Very Large Scale Integration (VLSI) circuits accumulators commonly exist with multipliers, this scheme can lead to minimum hardware overhead and performance degradation by reusing available accumulators to generate test vectors and compact test responses. Moreover, this scheme can achieve the goal of short test sequences and high fault coverage.