Abstract: Power consumption is a key issue in digital circuit design. The reliability of circuits becomes one of main challenges for low supply voltage design. Markov random field (MRF) circuits, which are the probabilistic-based approaches with energy based point of view, can achieve high noise immunity in ultra-low supply. However the traditional MRF elements have complex structures which become a stringent limitation factor for the application of MRF-based circuits in VLSI design. In this paper, we present a partial MRF (PMRF) clique energy design method for multi-logic elements, which can be referred to complementary PMRF pair. The proposed structure compensates the performance loss and achieves the area and complexity reduction. A full carry-look-ahead adder is implemented by using our proposed PMRF-pairs on the 65 nm TSMC CMOS technology. The measurement results show that the PMRF-pairs design can achieve higher fault-tolerance while occupying 29% area-saving, 86% energy-saving and 20% performance improvement compared with the complete MRF design.