A radiation hardened 16-Bit 25 MS/s pipeline ADC

A radiation hardened 16-bit 25 MS/s pipeline analog-to-digital (ADC) is designed. The architecture of pipeline with 4-bit first stage has been determined based on the consideration of nonideality such as capacitor mismatch and so on, and a novel bootstrapped switch is designed to improve the linearity. A switched-capacitor dynamic bias is proposed to lower the power consumption of the ADC by reducing the average current of amplifier. To meet the requirement of radiation hardness, a radiation hardened reinforcement design of the circuit is implemented according to the mechanism of total ionizing dose and single-event latch-up. This radiation hardened ADC is fabricated in 0.18 μm CMOS process and has area of 2.5 mm². After irradiation and with the 25 MHz sampling rate, 1.8 V power supply and 30.1 MHz sine input, the ADC achieves SNR (signal noise ratio) of 76.7 dBFS, SFDR (spurious-free dynamic range) of 95.1 dBFS, power consumption of 38.6 mW, while the ability of radiation hardness for total ionizing dose is 100 Krad(Si) and the threshold of single-event latch-up is 75 MeV•cm²/mg, which is suitable for space applications.