High consistency adaptive ramp circuit design for CMOS image sensors

This paper proposes a high consistency adaptive ramp circuit design method based on distributed integral type to address the inconsistency problem caused by parasitic backend wiring between multiple ramp generators and multiple columns in large-array CMOS image sensors (CIS). By analyzing the root causes of error introduction, a high-precision compensation technology combining average voltage technology, adaptive negative feedback dynamic adjustment technology, and digital correlation double sampling technology was adopted to complete the design of ramp signal inconsistency calibration scheme. The experimental results indicate that compared to existing global ramp and block-based multi-ramp approaches, the ramp generation circuit proposed in this paper achieves high accuracy of ramp signals with a DNL of +0.000636 LSB/−0.0006 LSB and an INL of +0.3292 LSB/−0.7386 LSB. The method reduces the inconsistency between the ramp signals to 0.4%LSB, decreases the column fixed pattern noise (CFPN) to 0.000037%, and increases the overall chip area and power consumption by only 0.6% and 0.5%, respectively. this approach offers an effective solution for the consistency of ramp signals in large-scale array CMOS image sensors.