Manchester编码器的FPGA设计与实现

详细信息

Design and FPGA Implementation of Manchester Encoder

State Key Laboratory of Broadband Optical Fiber Transmission and Communication Networks,UEST of China Chengdu 610054

摘要: 介绍一种用现场可编程门阵列FPGA实现Manchester编码器的VHDL设计方案,给出了一些重要模块的VHDL源代码。该设计方案已经用QuartusⅡ综合通过,并适配到具体的FPGA器件APEX20KE系列,时序仿真结果与理论相吻合,时序分析表明数据传输率可达22.5 Mb/s。
- 曼彻斯特编码器 /
- 硬件描述语言 /
- 现场可编程门阵列 /
- 综合 /
- 仿真
Abstract: This paper presents a VHDL project of Manchester encoder with FPGA implementation and releases VHDL source code of some important modules. Using QuartusⅡ2.1 of Altera company, the project has been synthesized and fitted to device APEX20KE series with speed. The result of timing simulation is accord with theory. And the timing analysis shows the data rate can be up to 22.5 Mbps.
- Manchester encoder /
- VHDL /
- FPGA /
- synthesis /
- simulation