OBS边缘节点接收调度模块的硬件实现

戴睿, 胡钢, 李扬

戴睿, 胡钢, 李扬. OBS边缘节点接收调度模块的硬件实现[J]. 电子科技大学学报, 2004, 33(6): 690-693,705.
引用本文: 戴睿, 胡钢, 李扬. OBS边缘节点接收调度模块的硬件实现[J]. 电子科技大学学报, 2004, 33(6): 690-693,705.
Dai Rui, Hu Gang, Li Yang. Hardware Implementation of the Scheduling Module in OBS Edge Node Receiver[J]. Journal of University of Electronic Science and Technology of China, 2004, 33(6): 690-693,705.
Citation: Dai Rui, Hu Gang, Li Yang. Hardware Implementation of the Scheduling Module in OBS Edge Node Receiver[J]. Journal of University of Electronic Science and Technology of China, 2004, 33(6): 690-693,705.

OBS边缘节点接收调度模块的硬件实现

基金项目: 

国家863计划资助项目(2002AA122021)

详细信息
    作者简介:

    戴睿(1980-),男,硕士生,主要从事光突发网络方面的研究.

  • 中图分类号: TN929.11

Hardware Implementation of the Scheduling Module in OBS Edge Node Receiver

  • 摘要: 给出了一种用于光突发交换网络中边缘节点接收调度模块的电路实现方案。该方案以基于虚拟输出队列机制的公平、高效的交换开关仲裁算法-输入串行为核心,利用两片高速现场可编程门阵列芯片,同时进行6路千兆光突发交换网络数据的接收、交换以及以太网封装。六路数据完全独立,并且两片现场可编程门阵列芯片之间可以相互通信。
    Abstract: In this paper, a hardware implementation scheme of the scheduling module in Optic burst switching(OBS) edge node receiver is presented. Input serial polling(ISP), which is based on virtual output queuing(VOQ) mechanism, is a kind of fair and high-performance algorithm for crossbar arbitrating. Focused on ISP, the design allows receiving, switching and Ethernet-assembling for 6 routs of 1 000M-OBS data with two high-speed FPGA chips. The 6 routs of data mentioned above are totally independent, and there exists communication between two FPGA chips.
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出版历程
  • 收稿日期:  2004-07-08
  • 刊出日期:  2004-12-14

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