锁相跳频源的极值相位裕量设计法

基金项目:

国防科工委预研基金项目

详细信息

Design of PLL Frequency Synthesizer by the Method of Extreme Value Phase Margin

摘要: 针对电流型电荷泵PLL频率综合器芯片,提出一种称为极值相位裕量的无源环路滤波器方案和设计方法。使PLL频率合成器成为2型(3~4)阶环;论证了设计公式,并用良好设计方法研制了一个L波段的跳频源。该跳频源在相位噪声、调频速度和杂散抑制等方面的性能指标较高。
- 锁相 /
- 频率综合器 /
- 滤波器 /
- 跳频源 /
- 相位裕量 /
- 相位噪声
Abstract: A passive loop filter scheme and the design method of the filter for current charge pump PLL frequency synthesizer chip are given in the paper. The method is known as the method of extreme value phase margin. Also, all design formula are proved. In fact, the PLL frequency synthesizer is 2 typeⅡ (3~4) order loop model. Using the method and formula above, a L-band synthesizer has been finished. It has satisfactory performance on phase noise, frequency jump speed and spur rejection.
- phase locked loop /
- frequency synthesizer /
- loop filter /
- frequency jump synthesizer /
- phase margin /
- phase noise