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兰州重离子加速器−冷却存储环是我国核科学领域的重大科学装置,其第二条放射性束流线上的实验终端用于开展重离子物理与交叉学科研究。外靶实验终端由一套谱仪组成,包含众多探测器,其中多丝漂移室(multi wire drift chamber, MWDC)探测器用于径迹测量,结合TOF墙可以实现粒子鉴别与径迹重建[1]。
MWDC探测器的读出电子学选用TOT方案来实现[2],其中放大甄别芯片选用SFE16,该芯片是CERN为COMPASS实验装置上的探测器设计的高集成度基于TOT技术的ASIC芯片[3],用于气体探测器探测X射线或带电粒子,并获得高精度的电荷测量、能量分辨和时间分辨。SFE16芯片集成了电荷灵敏前放与滤波成形、甄别和伪差分驱动输出等模块,并可配置多种增益与阈值模式,能满足多种实验测量的需求。利用该系统已经完成了多个物理实验,并取得了相应的物理成果[4-5]。
为进一步提高前端读出电子学的集成度和密度,并解决由于设备升级,而原有的电子学慢控配置模块老旧,无法兼容新设备,且配置效率较低这一紧迫的问题。本文对前端板进行升级,增加单板上SFE16芯片的数量,扩展单板通道数至32通道;并设计基于现场可编程门阵列(field programmable gate array, FPGA)的慢控配置模块,实现对SFE16芯片高效配置。
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通过上位机配置主放放大增益为20倍、极零相消测试点正常输出,配置完成后在前端挑选对应的测试点,通过示波器测量发现输出波形的信息与配置指令相符合,表示芯片配置成功。
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实验室测试框图如图8所示。测试使用的信号源为Tektronix公司的AFG3252C[16],AFG3252C通过编辑使其输出前沿20 ns、后沿1 ms的指数衰减信号,经过电荷注入板转化为电荷信号后送入FEE板信号注入端。SFE16芯片参数设置为:两级滤波成形后的信号的达峰时间是60 ns,主放放大倍数是20,DAC输出阈值为7.9 fC,输入电荷量范围为14~400 fC,过阈时间(TOT)与输入电荷量的关系如图9所示,可以看到TOT随着电荷量的增加而增大,但增加速率逐渐变慢,在电荷量大于100 fC时,输出的TOT与输入电荷量近似线性相关。输出的TOT的RMS值与输入电荷量的关系如图10所示,在14~400 fC的范围内,TOT的RMS值优于1.14 ns。单板通道间一致性结果如表1、表2所示,芯片内一致性优于芯片间。前端板单通道功耗为53 mW。
表 1 同一片SFE16的一致性测试结果
注入电荷量/fC 最大TOT误差/ns 100 2.2 400 1.0 表 2 不同片SFE16的一致性测试结果
注入电荷量/fC 最大TOT误差/ns 100 3.0 400 1.3
Upgrade of Front-End Electronics for CSR External Target Track Detector
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摘要: 多丝漂移室(MWDC)用于兰州重离子加速器−冷却存储环上外靶实验终端的径迹测量,其前端电子学中放大芯片采用SFE16芯片,目前前端电子学单板通道数较少,且慢控配置模块老旧,无法兼容新设备,配置效率较低。该文对前端板(FEE)进行升级,单板实现32通道;并设计一种基于现场可编程门阵列(FPGA)的配置板,通过上位机USB接口实现对多块SFE16芯片的快速高效配置。电子学测试实验结果表明,升级后的前端电子学在增加通道数的基础上保证了原有性能,并实现单次对248片SFE16芯片的配置,使用简单,配置效率高,实用性好。Abstract: The multi wire drift chamber (MWDC) is used for track measurement of the external target experimental terminal at heavy ion research facility in Lanzhou-Cooler storage ring. The amplification chip in the front-end electronics (FEE) adopts SFE16 chip. At present, the number of single board channels in the front-end electronics is few; In addition, the slow control configuration module is obsolete and cannot be compatible with new devices, resulting in low configuration efficiency. Therefore, the FEE is upgraded in this paper, and the single board realizes 32 channels; and a configuration board based on field programmable gate array (FPGA) is designed to realize fast and efficient configuration of multiple SFE16 chips through USB interface of host computer. The electronics test results show that the upgraded FEE guarantees the original performance on the basis of increasing the number of channels, and realizes the configuration of 248 SFE16 chips at a time. It is simple to use, efficient to configure, and practical.
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Key words:
- FPGA /
- host computer /
- MWDC /
- SFE16 /
- track measurement
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表 1 同一片SFE16的一致性测试结果
注入电荷量/fC 最大TOT误差/ns 100 2.2 400 1.0 表 2 不同片SFE16的一致性测试结果
注入电荷量/fC 最大TOT误差/ns 100 3.0 400 1.3 -
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