Research on Energy-Efficient Compact FFT Processor for 802.11p
-
摘要: 符合802.11p协议标准的基带与射频芯片是车载无线宽带通信系统的核心,其性能直接决定了车载无线宽带通信系统的性能。快速傅里叶变换(FFT)处理器是决定无线基带芯片性能的核心电路,该文通过分析FFT算法的特点,设计了一种用于802.11p的低功耗紧凑型64点处理器。该FFT处理器采用块浮点运算技术与单蝶形并行结构,极大地提高了FFT处理器的数据运算精度与运算速度。
-
[1] DIONYSIOS R, NIKOLAOS V. Conflict-Free parallel memory accessing techniques for FFT architectures[J]. IEEE Transactions on Circuits and Systems-I: Regular Papers, 2008, 55(11): 3438-3447. [2] CHIA H.Y, TSUNG H. Y, DEJAN M. Power and area minimization of reconfigurable FFT processors: a 3GPP-LTE example[J]. IEEE Journal of Solid-State Circuits, 2012, 47(3): 757-768. [3] XIN X, ERDAL O, JAFAR S. An efficient fft engine with reduced addressing logic[J]. IEEE Transactions on Circuits and Systems-II: Express Briefs, 2008, 55(11): 1149-1153. [4] LINKAI W, XIAO F Z, GERALD E, et al. Generic mixed-radix FFT PRUNING[J]. IEEE Signal Processing Letters, 2012, 19(3): 167-170. [5] MANOHAR A, MICHAEL B, KESHAB K P. Pipelined parallel FFT architectures via folding transformation[J]. IEEE Transactions on Very Large Scale Integration(VLSI) Systems, 2012, 20(6): 1068-1081. [6] SHIN Y L, CHIN L W, MING D S. Low-cost FFT processor for DVB-T2 applications[J]. IEEE Transactions on Consumer Electronics, 2010, 56(4): 2072-2079. [7] CHAO M C, CHIEN C H, YUAN H H. An energy-efficient partial FFT processor for the OFDMA communication system[J]. IEEE Transactions on Circuits and Systems-II: Express Briefs, 2010, 57(2): 136-140. [8] YUN N C. An efficient VLSI architecture for normal I/O order pipeline FFT design[J]. IEEE Transactions on Circuits and Systems-II: Express Briefs, 2008, 55(12): 1234-1238. [9] SONG N. T, CHI H L, TSIN Y C. An area-and energy-efficient multimode FFT processor for WPAN/WLAN/WMAN systems[J]. IEEE Journal of Solid-State Circuits, 2012, 47(6): 1419-1435. [10] MARK L, SANJAY R. A 0.13-μm 1-GS/s CMOS discrete-time FFT processor for ultra-Wideband OFDM wireless receivers[J]. IEEE Transactions on Microwave Theory and Techniques, 2011, 59(6): 1639-1650. [11] LIN C T, YU Y C, FAN L D. A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application[C]//IEEE International Conference Circuits System. [S.l.]: IEEE, 2006. [12] MAGAR S, SHEN S, LUI K G, et al. An application specific DSP chip set for 100 MHz data rates[C]// International Conference Acoustics, Speech, and Signal Processing. [S.l.]: [s.n.], 1988. [13] JO B G, SUNWOO M H. New continuous-flow mixed-radix (CFMR) FFT processor using novel in-place strategy[J]. IEEE Transactions on Circuits and Systems-I: Regular Papers, 2005, 52(5): 911-919. [14] HE S, TORKELSON M. Designing pipeline FFT processor for OFDM (de)modulation[C]//International Symposium on Signals, Systems, and Electronics. [S.l.]: [s.n.], 1998. [15] LEE S, PARK S C. Modified SDF architecture for mixed DIF/DIT FFT[C]//International Conference on Communication Technology. [S.l.]: [s.n.], 2006. [16] HE S, TORKELSON M. Design and implementation of a 1 024-point pipeline FFT processor[C]//IEEE Custom Integrated Circuits Conference (CICC'98). [S.l.]: IEEE, 1998. [17] BRIEN J O, MATHER J, HOLLAND B. A 200 MIPS single-chip 1k FFT processor[C]//IEEE International Solid-State Circuits Conference, Digest of Technical Papers. [S.l.]: IEEE, 1989. [18] BAAS B M. A low-power high-performance 1 024-point FFT processor[J]. IEEE Journal of Solid-State Circuits, 1999, 34(3): 380-387.
点击查看大图
计量
- 文章访问数: 4124
- HTML全文浏览量: 126
- PDF下载量: 130
- 被引次数: 0