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Article Navigation >  Journal of University of Electronic Science and Technology of China  > 2010  >  39(4): 528-531,536

LIU Jian, CHEN Jie, AO Tian-yong, XU Han-jing. Implementations of Synchronization and Communication in Heterogeneous Multi-Core DSP[J]. Journal of University of Electronic Science and Technology of China, 2010, 39(4): 528-531,536. doi: 10.3969/j.issn.1001-0548.2010.04.011
Citation: LIU Jian, CHEN Jie, AO Tian-yong, XU Han-jing. Implementations of Synchronization and Communication in Heterogeneous Multi-Core DSP[J]. Journal of University of Electronic Science and Technology of China, 2010, 39(4): 528-531,536. doi: 10.3969/j.issn.1001-0548.2010.04.011
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Implementations of Synchronization and Communication in Heterogeneous Multi-Core DSP

doi: 10.3969/j.issn.1001-0548.2010.04.011
  • 1.

    Institute of Microelectronics,Chinese Academy of Sciences Chaoyang Beijing 100029;

  • 2.

    School of Physics and Electronics,Henan University Kaifeng Henan 475001

  • Received Date: 2009-01-19
  • Rev Recd Date: 2009-06-12
  • Publish Date: 2010-08-15
  • A hardware semaphore module is designed to support the synchronization primitives, such as mutex and barrier. Compared with the atomic instruction realization, the method executes efficiently and uses fewer instructions. Based on the structure of scratch-pad memory, a shared program memory with two addressing mode of absolute address mapping and virtual address mapping is designed to implement instruction space sharing, resulting in higher utility of memory. The result of FPGA simulation demonstrates that, the performance of the proposed design can achieve speed-up 14.7% compared with traditional shared L2 caches.
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  • 1. 

    沈阳化工大学材料科学与工程学院 沈阳 110142

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Implementations of Synchronization and Communication in Heterogeneous Multi-Core DSP

doi: 10.3969/j.issn.1001-0548.2010.04.011
  • 1. Institute of Microelectronics,Chinese Academy of Sciences Chaoyang Beijing 100029;
  • 2. School of Physics and Electronics,Henan University Kaifeng Henan 475001
  • Received Date: 2009-01-19
  • Rev Recd Date: 2009-06-12
  • Publish Date: 2010-08-15

Abstract: A hardware semaphore module is designed to support the synchronization primitives, such as mutex and barrier. Compared with the atomic instruction realization, the method executes efficiently and uses fewer instructions. Based on the structure of scratch-pad memory, a shared program memory with two addressing mode of absolute address mapping and virtual address mapping is designed to implement instruction space sharing, resulting in higher utility of memory. The result of FPGA simulation demonstrates that, the performance of the proposed design can achieve speed-up 14.7% compared with traditional shared L2 caches.

LIU Jian, CHEN Jie, AO Tian-yong, XU Han-jing. Implementations of Synchronization and Communication in Heterogeneous Multi-Core DSP[J]. Journal of University of Electronic Science and Technology of China, 2010, 39(4): 528-531,536. doi: 10.3969/j.issn.1001-0548.2010.04.011
Citation: LIU Jian, CHEN Jie, AO Tian-yong, XU Han-jing. Implementations of Synchronization and Communication in Heterogeneous Multi-Core DSP[J]. Journal of University of Electronic Science and Technology of China, 2010, 39(4): 528-531,536. doi: 10.3969/j.issn.1001-0548.2010.04.011
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