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SHEN Jian-liang, YAN Ming, LI Si-kun, LIU Lei. Design and Implementation of Embedded Visual Media Process SoC with Hierarchy on-Chip Bus Architecture[J]. Journal of University of Electronic Science and Technology of China, 2011, 40(6): 898-904. doi: 10.3969/j.issn.1001-0548.2011.06.018
Citation: SHEN Jian-liang, YAN Ming, LI Si-kun, LIU Lei. Design and Implementation of Embedded Visual Media Process SoC with Hierarchy on-Chip Bus Architecture[J]. Journal of University of Electronic Science and Technology of China, 2011, 40(6): 898-904. doi: 10.3969/j.issn.1001-0548.2011.06.018
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Design and Implementation of Embedded Visual Media Process SoC with Hierarchy on-Chip Bus Architecture

doi: 10.3969/j.issn.1001-0548.2011.06.018
  • 1.

    School of Computer,National University of Defense Technology Changsha 410073

  • Received Date: 2011-06-10
  • Rev Recd Date: 2011-09-24
  • Publish Date: 2011-12-15
  • In order to meet the high demand of computation intensive and band-width exhausting media applications for embedded system, a heterogeneous multi-core embedded visual media processor, named EVMPSoC, is proposed. The chip consists of a main processor called EPStar3, which is a 32 bit RISC embedded processor, and two SIMD coprocessor, which are designed by application-specific instruction set. According to the communication characteristics of media applications, the hierachy high/low speed bus and dual band-width parallel memory access with multi-channel are used as the on-chip bus Architecture of EVMPSoC. The chip was taped out sucessful using SMIC 0.13 μm LVT CMOS technology and packaged by Amkor with PBGA 400. It runs well at peak frequency 416 MHz, and shows its high efficiency and avaliability.
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  • 1. 

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Design and Implementation of Embedded Visual Media Process SoC with Hierarchy on-Chip Bus Architecture

doi: 10.3969/j.issn.1001-0548.2011.06.018
  • 1. School of Computer,National University of Defense Technology Changsha 410073
  • Received Date: 2011-06-10
  • Rev Recd Date: 2011-09-24
  • Publish Date: 2011-12-15

Abstract: In order to meet the high demand of computation intensive and band-width exhausting media applications for embedded system, a heterogeneous multi-core embedded visual media processor, named EVMPSoC, is proposed. The chip consists of a main processor called EPStar3, which is a 32 bit RISC embedded processor, and two SIMD coprocessor, which are designed by application-specific instruction set. According to the communication characteristics of media applications, the hierachy high/low speed bus and dual band-width parallel memory access with multi-channel are used as the on-chip bus Architecture of EVMPSoC. The chip was taped out sucessful using SMIC 0.13 μm LVT CMOS technology and packaged by Amkor with PBGA 400. It runs well at peak frequency 416 MHz, and shows its high efficiency and avaliability.

SHEN Jian-liang, YAN Ming, LI Si-kun, LIU Lei. Design and Implementation of Embedded Visual Media Process SoC with Hierarchy on-Chip Bus Architecture[J]. Journal of University of Electronic Science and Technology of China, 2011, 40(6): 898-904. doi: 10.3969/j.issn.1001-0548.2011.06.018
Citation: SHEN Jian-liang, YAN Ming, LI Si-kun, LIU Lei. Design and Implementation of Embedded Visual Media Process SoC with Hierarchy on-Chip Bus Architecture[J]. Journal of University of Electronic Science and Technology of China, 2011, 40(6): 898-904. doi: 10.3969/j.issn.1001-0548.2011.06.018
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