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HU Jian-hao, TANG Qing. Fault-Tolerance Computing Architecture Design for Low Suppling Voltage[J]. Journal of University of Electronic Science and Technology of China, 2013, 42(6): 831-835. doi: 10.3969/j.issn.1001-0548.2013.06.004
Citation: HU Jian-hao, TANG Qing. Fault-Tolerance Computing Architecture Design for Low Suppling Voltage[J]. Journal of University of Electronic Science and Technology of China, 2013, 42(6): 831-835. doi: 10.3969/j.issn.1001-0548.2013.06.004
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Fault-Tolerance Computing Architecture Design for Low Suppling Voltage

doi: 10.3969/j.issn.1001-0548.2013.06.004
  • 1.

    National Key Laboratory of Science and Technology on Communications,University of Electronic Science and Technology of China Chengdu 611731

  • Received Date: 2012-05-10
  • Rev Recd Date: 2013-07-10
  • Publish Date: 2013-12-15
  • In order to achieve low power consumption, the supply voltage is reduced gradually but this increases the probabilistic characteristic of digital circuits. In this paper, we propose the design method which combines of the reduced precision redundancy (RPR) algorithm with triple-modular redundancy (TMR) algorithm and Redundant residue number systems (RRNS) algorithm, referred as RPR-TMR and RPR-RRNS architectures respectively. The performance of these two kinds of structures is designed and analyzed. The results of case study show that the proposed of architectures can archive low power consumption and high output SNR.
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    沈阳化工大学材料科学与工程学院 沈阳 110142

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Fault-Tolerance Computing Architecture Design for Low Suppling Voltage

doi: 10.3969/j.issn.1001-0548.2013.06.004
  • 1. National Key Laboratory of Science and Technology on Communications,University of Electronic Science and Technology of China Chengdu 611731
  • Received Date: 2012-05-10
  • Rev Recd Date: 2013-07-10
  • Publish Date: 2013-12-15

Abstract: In order to achieve low power consumption, the supply voltage is reduced gradually but this increases the probabilistic characteristic of digital circuits. In this paper, we propose the design method which combines of the reduced precision redundancy (RPR) algorithm with triple-modular redundancy (TMR) algorithm and Redundant residue number systems (RRNS) algorithm, referred as RPR-TMR and RPR-RRNS architectures respectively. The performance of these two kinds of structures is designed and analyzed. The results of case study show that the proposed of architectures can archive low power consumption and high output SNR.

HU Jian-hao, TANG Qing. Fault-Tolerance Computing Architecture Design for Low Suppling Voltage[J]. Journal of University of Electronic Science and Technology of China, 2013, 42(6): 831-835. doi: 10.3969/j.issn.1001-0548.2013.06.004
Citation: HU Jian-hao, TANG Qing. Fault-Tolerance Computing Architecture Design for Low Suppling Voltage[J]. Journal of University of Electronic Science and Technology of China, 2013, 42(6): 831-835. doi: 10.3969/j.issn.1001-0548.2013.06.004
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