[1]
|
BAUMANN R C. Radiation-induced soft errors in advanced semiconductor technologies[J]. IEEE Transactions on Device and Materials Reliability, 2005, 5(3):305-316. doi: 10.1109/TDMR.2005.853449 |
[2]
|
PETERSEN E, KOGA R, SHOGA M A, et al. The single event revolution[J]. IEEE Transactions on Nuclear Science, 2013, 60(3):1824-1835. doi: 10.1109/TNS.2013.2248065 |
[3]
|
ZHU X W, DENG X W, BAUMANN R, et al. A quantitative assessment of charge collection efficiency of N+ and P+ diffusion areas in terrestrial neutron environment[J]. IEEE Transactions on Nuclear Science, 2007, 54(6):2156-2161. doi: 10.1109/TNS.2007.908758 |
[4]
|
刘必慰,郝跃,陈书明. SEU加固存储单元中的多节点翻转[J]. 半导体学报,2008, 29(2):244-250. http://www.cnki.com.cn/Article/CJFDTOTAL-BDTX200802010.htm
LIU Bi-Wei, HAO Yao, CHEN Shu-min. Multiple node upset in SEU hardened storage cells[J]. Journal of Semiconductors, 2008, 29(2):244-250. http://www.cnki.com.cn/Article/CJFDTOTAL-BDTX200802010.htm |
[5]
|
BLACK J D, DODD P E, WARREN K M. Physics of multiple-node charge collection and impacts on single-event characterization and soft error rate prediction[J]. IEEE Transactions on Nuclear Science, 2013, 60(3):1836-1851. doi: 10.1109/TNS.2013.2260357 |
[6]
|
BLACK J D, BALL D R, ROBINSON W H, et al. Characterizing SRAM single event upset in terms of single and double node charge collection[J]. IEEE Transactions on Nuclear Science, 2008, 55(6):2943-2947. doi: 10.1109/TNS.2008.2007231 |
[7]
|
CALIN T, NICOLAIDIS M, VELAZCO R. Upset hardened memory design for submicron CMOS technology[J]. IEEE Transactions on Nuclear Science, 1996, 43(6):2874-2878. doi: 10.1109/23.556880 |
[8]
|
FAZELI M, PATOOGHY A, MIREMADI S G, et al. Feedback redundancy:a power efficient SEU-tolerant latch design for deep sub-micron technologies[C]//37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks. Edinburgh, UK:IEEE, 2007:276-285. |
[9]
|
NAN H Q, CHOI K. High performance, low cost, and robust soft error tolerant latch designs for nanoscale CMOS technology[J]. IEEE Transactions on Circuits and Systems, 2012, 59(7):1445-1457. doi: 10.1109/TCSI.2011.2177135 |
[10]
|
RAJAEI R, TABANDEH M, RASHIDIAN B. Single event upset immune latch circuit design using C-element[C]//2011 IEEE 9th International Conference on ASIC.[S.l]:IEEE, 2011:252-255. |
[11]
|
ZHANG C Y, WANG Z S. A novel reliable SEU hardened latch to mitigate multi-node charge collecrion[C]//IET Internation Conference on Information Science and Control Engineering. Shenzhen, China:IET, 2012:1-4. |
[12]
|
ALESSIO M D, OTTAVI M, LOMBARDI F. Design of a nanometric CMOS memory cell for hardening to a single event with a multiple-node upset[J]. IEEE Transactions on Device and Materials Reliability, 2014, 14(1):127-132. doi: 10.1109/TDMR.2012.2206814 |
[13]
|
CASEY M C, BHUVA B L, BLACK J D, et al. Single-event tolerant latch using cascode-voltage switch gates[J]. IEEE Transactions on Nuclear Science, 2006, 53(6):3386-3391. doi: 10.1109/TNS.2006.884970 |
[14]
|
WEY I C, YANG Y S, WU B C, et al. A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design[J]. Microelectronics Journal, 2014(45):1-13. http://cn.bing.com/academic/profile?id=1982484741&encoded=0&v=paper_preview&mkt=zh-cn |
[15]
|
NICOLAIDIS M. Time redundancy based soft-error tolerance to rescue nanometer technologies[C]//17th IEEE VLSI Test Symposium. Dana Point, CA, USA:IEEE, 1999:86-94. |
[16]
|
KATSAROU K, TSIATOUHAS Y. Double node charge sharing SEU tolerant latch design[C]//IEEE 20th Internation On-Line Testing Symposium (IOLTS). Platja d'Aro, Girona:IEEE, 2014:122-127. |
[17]
|
LIU B W, CHEN S M, LIANG B, et al. Temperature dependncy of charge sharing and MBU sensitivity in 130 nm CMOS technology[J]. IEEE Transactions on Nuclear Science, 2009, 56(4):2473-2479. doi: 10.1109/TNS.2009.2022267 |
[18]
|
RAJAEI R, TABANDEH M, FAZELI M. Single event multiple upset (SEMU) tolerant latch designs in presence of process and temperature variations[J]. Journal of Circuits, Systems and Computers, 2015, 24(01):1550007. doi: 10.1142/S0218126615500073 |
[19]
|
NAN H Q, CHOI K. Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology[J]. Microelectronics Reliability, 2011(51):2086-2092. http://cn.bing.com/academic/profile?id=1971440286&encoded=0&v=paper_preview&mkt=zh-cn |