Research on the Impact of Trapped Charges at SiC/SiO<sub>2</sub> Interface on the Short-circuit Performances of SiC MOSFET

ZHOU Yu-ming; MU Shi-lu; JIANG Bao-guo; WANG Bing; CHEN Zhao-quan

doi:10.3969/j.issn.1001-0548.2019.06.021

Volume 48 Issue 6

Nov. 2019

Article Contents

Article Navigation > Journal of University of Electronic Science and Technology of China > 2019 > 48(6): 947-953

ZHOU Yu-ming, MU Shi-lu, JIANG Bao-guo, WANG Bing, CHEN Zhao-quan. Research on the Impact of Trapped Charges at SiC/SiO2 Interface on the Short-circuit Performances of SiC MOSFET[J]. Journal of University of Electronic Science and Technology of China, 2019, 48(6): 947-953. doi: 10.3969/j.issn.1001-0548.2019.06.021

Citation:

ZHOU Yu-ming, MU Shi-lu, JIANG Bao-guo, WANG Bing, CHEN Zhao-quan. Research on the Impact of Trapped Charges at SiC/SiO₂ Interface on the Short-circuit Performances of SiC MOSFET[J]. Journal of University of Electronic Science and Technology of China, 2019, 48(6): 947-953. doi: 10.3969/j.issn.1001-0548.2019.06.021

Research on the Impact of Trapped Charges at SiC/SiO₂ Interface on the Short-circuit Performances of SiC MOSFET

doi: 10.3969/j.issn.1001-0548.2019.06.021

Anhui Provincial Key Laboratory of Power Electronics and Motion Control, Anhui University of Technology Maanshan Anhui 243002

Received Date: 2018-10-24
Rev Recd Date: 2019-03-08
Publish Date: 2019-11-30

Abstract

The decrease in the trapped charges at SiC/SiO₂ interface is helpful to lower the on-state resistance and switching loss of SiC MOSFET, however, the lift of channel current brings higher current stress to SiC MOSFET during short-circuit case. On the basis of the traditional equivalent circuit model for SiC MOSFET, a short-circuit failure model of SiC MOSFET has been developed. The model introduces the leakage current across the PN junction between N-drift region and P base region of SiC MOSFET, and employs an advance carrier mobility model with the trapped charges at the SiC/SiO₂ interface. By the developed failure model, the influence brought by the interface trapped charges on the short-circuit performances has been exploited, and the result shows that the reduction of interface trapped charge shortens the time of SiC MOSFET withstanding short-circuit stress. Further, the mechanism of interface trapped charges affecting the short-circuit withstanding time has been discussed by separating the leakage current components from the failure current.
- carrier mobility,
- current stress,
- interface trapped charge,
- leakage current,
- SiC MOSFET

References

[1]	张林, 肖剑, 邱彦章, 等. Ni/4H-SiC SBD电离辐照探测器的实验研究[J].电子科技大学学报, 2012, 41(3):467-470. doi: 10.3969/j.issn.1001-0548.2012.03.028 ZHANG Lin, XIAO Jian, QIU Yan-zhang, et al. Experiment study of Ni/4H-SiC Schottky diode ionization radiation detector[J]. Journal of University of Electronic Science and Technology of China, 2012, 41(3):467-470. doi: 10.3969/j.issn.1001-0548.2012.03.028
[2]	周郁明, 靳爱津, 冯德仁.钒补偿度对SiC光导开关特性影响的研究[J].电子科技大学学报, 2012, 41(6):937-940. http://www.juestc.uestc.edu.cn/CN/abstract/abstract1466.shtml ZHOU Yu-ming, JIN Ai-jin, FENG De-ren. Simulation of vanadium doped concentration on the effect of characteristics of SiC photoconducting switches[J]. Journal of University of Electronic Science and Technology of China, 2012, 41(6):937-940. http://www.juestc.uestc.edu.cn/CN/abstract/abstract1466.shtml
[3]	CECCARELLI L, REIGOSA P D, IANNUZZO F, et al. A survey of SiC power MOSFETs short-circuit robustness and failure mode analysis[J]. Microelectronics Reliability, 2017, 76-77:272-276. doi: 10.1016/j.microrel.2017.06.093
[4]	NAMAI M, AN J, YANO H, et al. Investigation of short-circuit failure mechanisms of SiC MOSFETs by varying DC bus voltage[J]. Japanese Journal of Applied Physics, 2018, 57(7):074102. doi: 10.7567/JJAP.57.074102
[5]	WANG Z, SHI X, TOLBERT L M, et al. Temperaturedependent short-circuit capability of silicon carbide power MOSFETS[J]. IEEE Transactions on Power Electronics, 2016, 31(2):1555-1566. doi: 10.1109/TPEL.2015.2416358
[6]	IONITA C, NAWAZ M, ILVES K. On the short-circuit and avalanche ruggedness reliability assessment of SiC MOSFET modules[J]. Microelectronics Reliability, 2017, 71:6-16. doi: 10.1016/j.microrel.2017.02.004
[7]	ROMANO G, FAYYAZ A, RICCIO M, et al. A comprehensive study of short-circuit ruggedness of silicon carbide power MOSFETS[J]. IEEE Journal of Emerging & Selected Topics in Power Electronics, 2016, 4(3):978-987. http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=10d2182619fcac7f0d5461ae7fc7b702
[8]	SCHROCK J A, PUSHPAKARAN B N, BILBAO A V, et al. Failure analysis of 1200-V/150-A SiC MOSFET under repetitive pulsed overcurrent conditions[J]. IEEE Transactions on Power Electronics, 2015, 31(3):1816-1821. http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=1175526a066ad0db0048354dcae6f511
[9]	TANIMOTO Y, SAITO A, MATSUURA K, et al. Power-loss prediction of high-voltage SiC-MOSFET circuits with compact model including carrier-trap influences[J]. IEEE Transactions on Power Electronics, 2016, 31(6):4509-4516. doi: 10.1109/TPEL.2015.2477413
[10]	ZHOU Y M, LIU H Z, YANG T T, et al. SPICE modeling of SiC MOSFET considering interface-trap influence[J]. CPSS Transactions on Power Electronics and Application, 2018, 3(1):56-64. doi: 10.24295/CPSSTPEA.2018.00006
[11]	周郁明, 刘航志, 杨婷婷, 等.碳化硅MOSFET的Matlab/Simulink建模及其温度特性评估[J].南京航空航天大学学报, 2017, 49(6):851-857. http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=njhkht201706015 ZHOU Yu-ming, LIU Hang-zhi, YANG Ting-ting, et al. Matlab/Simulink modeling and temperature characteristics evaluation of SiC MOSFET[J]. Journal of Nanjing University of Aeronautics & Astronautics, 2017, 49(6):851-857. http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=njhkht201706015
[12]	孙凯, 陆珏晶, 吴红飞, 等.碳化硅MOSFET的变温度参数建模[J].中国电机工程学报, 2013, 33(3):37-43. http://d.old.wanfangdata.com.cn/Periodical/zgdjgcxb201303005 SU Kai, LU Ju-jing, WU Hong-fei, et al. Modeling of SiC MOSFET with temperature dependent parameters[J]. Proceedings of the CSEE, 2013, 33(3):540-544. http://d.old.wanfangdata.com.cn/Periodical/zgdjgcxb201303005
[13]	WANG J, ZHOU X H, Li J, et al. 10-kV SiC MOSFET-based boost converter[J]. IEEE Transactions on Industrial Application. 2009, 45(6):2056-2063. doi: 10.1109/TIA.2009.2031915
[14]	周郁明, 刘航志, 杨婷婷, 等. SiC JFET与SiC MOSFET失效模型及其短路特性对比[J].电子学报, 2019, 47(3):726-733. http://d.old.wanfangdata.com.cn/Periodical/dianzixb201903030 ZHOU Yu-ming, LIU Hang-zhi, YANG Ting-ting, et al. Failure models and comparison in short-circuit performances for SiC JFET and SiC MOSFET[J]. Acta Electronica Sinica, 2019, 47(3):726-733. http://d.old.wanfangdata.com.cn/Periodical/dianzixb201903030
[15]	PÉREZ-TOMÁS A, BROSSELARD P, GODIGNON P, et al. Field-effect mobility temperature modeling of 4H-SiC metal-oxide-semiconductor transistors[J]. Journal of Applied Physics, 2006, 100(11):114508. doi: 10.1063/1.2395597
[16]	周郁明, 李勇杰, 鲍观甲, 等.基于先进迁移率模型的4H-SiC MOSFET Spice模型研究[J].中国科学技术大学学报, 2017, 47(10):878-884. doi: 10.3969/j.issn.0253-2778.2017.10.011 ZHOU Yu-ming, LI Yong-jie, BAO Guan-jia, et al. Spice modeling of 4H-SiC MOSFET based on advanced mobility model[J]. Journal of University of Science and Technology of China, 2017, 47(10):878-884. doi: 10.3969/j.issn.0253-2778.2017.10.011
[17]	ROZEN J, DHAR S, ZVANUT M E, et al. Density of interface states, electron traps, and hole traps as a function of the nitrogen density in SiO₂ on SiC[J]. Journal of Applied Physics, 2009, 105(12):658-662. http://www.wanfangdata.com.cn/details/detail.do?_type=perio&id=40b5d3472e303d251ff177925fbc65e5

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与硅(Si)基功率半导体器件相比，碳化硅(SiC)功率半导体器件具有工作频率高、开关损耗低、体积小等诸多优点^[1-2]。在工业应用场合，尤其是在电机驱动系统中，短路事件时有发生，这种情况下功率器件承受了比正常状态下高得多的电流应力。由于相同功率等级下，单个SiC功率器件芯片面积比Si功率器件小，因而遭遇短路故障时SiC MOSFET比Si MOSFET更容易失效。

目前，不少工作对SiC MOSFET在短路环境下的特性进行了深入地研究。文献[3-4]采用数值模拟和实验相结合的方法研究了1.2 kV的SiC MOSFET的短路失效机理。文献[5]采用二维有限元数值模拟了SiC MOSFET的“热奔”失效模式。文献[6]对比了不同型号的商业化SiC MOSFET的短路特性。文献[7-8]采用半导体器件计算机模拟(TCAD)的方法研究了SiC MOSFET在短路状态下器件内部的温度分布。这些文献的研究结果，对于正确认识SiC MOSFET在短路故障情况下发生失效的起因、应用时选择正确的SiC MOSFET型号以及在SiC MOSFET保护电路的设计等方面都有积极意义。

SiC MOSFET区别于Si MOSFET的一个显著特点是在SiC/SiO₂界面处存在着密度高达10¹² cm^-2·eV^-1的界面态陷阱，比Si/SiO₂界面态陷阱密度高出两个数量级。

界面态陷阱能够俘获N型MOSFET沟道中的自由电子，形成呈负电性的界面态电荷，这种行为导致沟道中自由电子数量减少、通态电阻增加；同时，呈负电性的界面态电荷对沟道中的自由电子具有电荷散射作用，阻碍了沟道中自由电子的运动、降低了自由电子的迁移率。文献[9-11]从理论和实验两个方面研究了界面态电荷对SiC MOSFET开关特性的影响，指出界面态电荷能够引起SiC MOSFET开通延迟、关断提前和开关损耗增加。

减少界面态电荷的数量能够提升SiC MOSFET的沟道电流，当SiC MOSFET在开关电路中突然遭遇短路事故时，势必将进一步抬升SiC MOSFET的沟道电流密度，因而界面态电荷能够影响SiC MOSFET处于短路状态下的生存时间。

本文以型号为C2M0080120D的SiC MOSFET (第二代碳化硅产品，1.2 kV/36 A)为参照对象，建立了SiC MOSFET在短路故障电路中的失效模型。该模型考虑了短路状态下SiC MOSFET结构中穿过N^-漂移区和P基区组成的PN结的泄漏电流，引入了包含界面态电荷的载流子迁移率，讨论了界面态电荷对SiC MOSFET处于短路状态下生存时间的影响，并通过分析界面态电荷对穿过PN结泄漏电流分量的影响因素，揭示了界面态电荷影响SiC MOSFET短路生存时间的机理。

3. 结束语

本文建立了SiC MOSFET在短路故障电路中的失效模型，引入了N^-漂移区和P基区之间PN结的泄漏电流，包含SiC/SiO₂界面态电荷的载流子迁移率模型。同时，本文在短路状态下验证了失效模型的准确性，讨论了界面态电荷对SiC MOSFET短路耐受能力的影响。

结果表明，SiC MOSFET的SiC/SiO₂界面态陷阱密度的减少降低了SiC MOSFET的短路耐受能力，这主要是由于界面态电荷的减少抬升了沟道电流密度，从而加速了短路状态下SiC MOSFET温度的上升，这导致了与温度有关的泄漏电流增加；泄漏电流的增加又抬升了SiC MOSFET器件内的温度。这种相互作用机制加速了SiC MOSFET的短路失效。

Reference (17)

[1]	张林, 肖剑, 邱彦章. Ni/4H-SiC SBD电离辐照探测器的实验研究[J]. 电子科技大学学报, 2012, 41(3): 467-470. doi: 10.3969/j.issn.1001-0548.2012.03.028	ZHANG Lin, XIAO Jian, QIU Yan-zhang. Experiment study of Ni/4H-SiC Schottky diode ionization radiation detector[J]. Journal of University of Electronic Science and Technology of China, 2012, 41(3): 467-470. doi: 10.3969/j.issn.1001-0548.2012.03.028
[2]	周郁明, 靳爱津, 冯德仁. 钒补偿度对SiC光导开关特性影响的研究[J]. 电子科技大学学报, 2012, 41(6): 937-940.	ZHOU Yu-ming, JIN Ai-jin, FENG De-ren. Simulation of vanadium doped concentration on the effect of characteristics of SiC photoconducting switches[J]. Journal of University of Electronic Science and Technology of China, 2012, 41(6): 937-940.
[3]	CECCARELLI L, REIGOSA P D, IANNUZZO F. A survey of SiC power MOSFETs short-circuit robustness and failure mode analysis[J]. Microelectronics Reliability, 2017, 76-77(): 272-276. doi: 10.1016/j.microrel.2017.06.093
[4]	NAMAI M, AN J, YANO H. Investigation of short-circuit failure mechanisms of SiC MOSFETs by varying DC bus voltage[J]. Japanese Journal of Applied Physics, 2018, 57(7): 074102-. doi: 10.7567/JJAP.57.074102
[5]	WANG Z, SHI X, TOLBERT L M. Temperaturedependent short-circuit capability of silicon carbide power MOSFETS[J]. IEEE Transactions on Power Electronics, 2016, 31(2): 1555-1566. doi: 10.1109/TPEL.2015.2416358
[6]	IONITA C, NAWAZ M, ILVES K. On the short-circuit and avalanche ruggedness reliability assessment of SiC MOSFET modules[J]. Microelectronics Reliability, 2017, 71(): 6-16. doi: 10.1016/j.microrel.2017.02.004
[7]	ROMANO G, FAYYAZ A, RICCIO M. A comprehensive study of short-circuit ruggedness of silicon carbide power MOSFETS[J]. IEEE Journal of Emerging & Selected Topics in Power Electronics, 2016, 4(3): 978-987.
[8]	SCHROCK J A, PUSHPAKARAN B N, BILBAO A V. Failure analysis of 1200-V/150-A SiC MOSFET under repetitive pulsed overcurrent conditions[J]. IEEE Transactions on Power Electronics, 2015, 31(3): 1816-1821.
[9]	TANIMOTO Y, SAITO A, MATSUURA K. Power-loss prediction of high-voltage SiC-MOSFET circuits with compact model including carrier-trap influences[J]. IEEE Transactions on Power Electronics, 2016, 31(6): 4509-4516. doi: 10.1109/TPEL.2015.2477413
[10]	ZHOU Y M, LIU H Z, YANG T T. SPICE modeling of SiC MOSFET considering interface-trap influence[J]. CPSS Transactions on Power Electronics and Application, 2018, 3(1): 56-64. doi: 10.24295/CPSSTPEA.2018.00006
[11]	周郁明, 刘航志, 杨婷婷. 碳化硅MOSFET的Matlab/Simulink建模及其温度特性评估[J]. 南京航空航天大学学报, 2017, 49(6): 851-857.	ZHOU Yu-ming, LIU Hang-zhi, YANG Ting-ting. Matlab/Simulink modeling and temperature characteristics evaluation of SiC MOSFET[J]. Journal of Nanjing University of Aeronautics & Astronautics, 2017, 49(6): 851-857.
[12]	孙凯, 陆珏晶, 吴红飞. 碳化硅MOSFET的变温度参数建模[J]. 中国电机工程学报, 2013, 33(3): 540-544.	SU Kai, LU Ju-jing, WU Hong-fei. Modeling of SiC MOSFET with temperature dependent parameters[J]. Proceedings of the CSEE, 2013, 33(3): 540-544.
[13]	WANG J, ZHOU X H, Li J. 10-kV SiC MOSFET-based boost converter[J]. IEEE Transactions on Industrial Application, 2009, 45(6): 2056-2063. doi: 10.1109/TIA.2009.2031915
[14]	周郁明, 刘航志, 杨婷婷. SiC JFET与SiC MOSFET失效模型及其短路特性对比[J]. 电子学报, 2019, 47(3): 726-733.	ZHOU Yu-ming, LIU Hang-zhi, YANG Ting-ting. Failure models and comparison in short-circuit performances for SiC JFET and SiC MOSFET[J]. Acta Electronica Sinica, 2019, 47(3): 726-733.
[15]	PÉREZ-TOMÁS A, BROSSELARD P, GODIGNON P. Field-effect mobility temperature modeling of 4H-SiC metal-oxide-semiconductor transistors[J]. Journal of Applied Physics, 2006, 100(11): 114508-. doi: 10.1063/1.2395597
[16]	周郁明, 李勇杰, 鲍观甲. 基于先进迁移率模型的4H-SiC MOSFET Spice模型研究[J]. 中国科学技术大学学报, 2017, 47(10): 878-884. doi: 10.3969/j.issn.0253-2778.2017.10.011	ZHOU Yu-ming, LI Yong-jie, BAO Guan-jia. Spice modeling of 4H-SiC MOSFET based on advanced mobility model[J]. Journal of University of Science and Technology of China, 2017, 47(10): 878-884. doi: 10.3969/j.issn.0253-2778.2017.10.011
[17]	ROZEN J, DHAR S, ZVANUT M E. Density of interface states, electron traps, and hole traps as a function of the nitrogen density in SiO₂ on SiC[J]. Journal of Applied Physics, 2009, 105(12): 658-662.

表达式	符号取值或表达式
${I_{{\rm{th}}}} = \frac{{qS{n_{\rm{i}}}}}{{{\tau _{\rm{g}}}}}\sqrt {\frac{{2{\varepsilon _{{\rm{SiC}}}}}}{q}\left( {\frac{{{N_{\rm{D}}} + {N_{\rm{A}}}}}{{{N_{\rm{A}}}{N_{\rm{D}}}}}} \right){V_{{\rm{DS}}}}} $	N_A=3.5×10¹⁷ cm^-3 N_D=7.5×10¹⁵ cm^-3 τ_g=2 ns S=0.124 cm² ${n_{\rm{i}}} = 1.7 \times {10^{16}}{T^{3/2}}{\operatorname{e} ^{ - 2.08 \times {{10}^4}/T}}{\rm{c}}{{\rm{m}}^{ - 3}}$
${I_{{\rm{diff}}}} = q{S_{}}\left( {\frac{{n_{\rm{i}}^{\rm{2}}{D_{\rm{n}}}}}{{{L_{\rm{n}}}{N_{\rm{A}}}}} + \frac{{n_{\rm{i}}^{\rm{2}}{D_{\rm{p}}}}}{{{L_{\rm{p}}}{N_{\rm{D}}}}}} \right)$	${D_{\rm{n}}} = \frac{{kT}}{q}{\mu _{\rm{n}}}$ ${D_{\rm{p}}} = \frac{{kT}}{q}{\mu _{\rm{p}}}$ ${L_{\rm{n}}} = \sqrt {{D_n}{\tau _{\rm{n}}}} {\rm{ }}$ ${L_{\rm{p}}} = \sqrt {{D_{\rm{p}}}{\tau _{\rm{p}}}} {\rm{ }}$
	${\alpha _{\rm{n}}} = 4.6 \times {10^5}\exp \left( { - \frac{{1.78 \times {{10}^7}}}{E}} \right){\rm{ c}}{{\rm{m}}^{ - 1}}$ ε_SiC=9.7×8.854×10^-14 F·cm^-1

分量	表达式	取值
μ_B	${\mu _{{\rm{min}}}} + \frac{{{\mu _{{\rm{max}}}} - {\mu _{{\rm{min}}}}}}{{1 + \frac{{N{}_{\rm{A}}}}{{{N_{{\rm{REF}}}}}}}}$	μ_max=950 cm²/V s μ_min=40 cm²/V s N_A=6×10¹⁷ cm^-3 N_REF=2×10¹⁷ cm^-3
μ_AC	$\frac{B}{{{E_ \bot }}} + \frac{{CN_{\rm{A}}^{{\rm{ \mathsf{ α} }}1}}}{{TE_ \bot ^{{\rm{1/3}}}}}$	B=1.0×10⁶ cm/s α1=0.0284 C=3.23×10⁶ K cm/s·(V/cm)^-2/3
μ_SR	$\frac{{{D_{\rm{1}}}}}{{E_ \bot ^2}}$	D₁=5.82×10¹⁴ cm²/V·s (V/cm)²
μ_C	$N{T^{\rm{ \mathsf{ α} }}}\frac{{Q_{{\rm{inv}}}^{\rm{ \mathsf{ β} }}}}{{{Q_{{\rm{trap}}}}}}$	α=1 β=1 N=0.007 525 cm²/V·s

热阻R_th/mK·W^-1	热容C_th/mJ·K^-1
R_th1=13.30	C_th1=0.424
R_th2=13.30	C_th2=0.341
R_th3=37.80	C_th3=1.320
R_th4=36.90	C_th4=1.580
R_th5=8.36	C_th5=1.880
R_th6=5.84	C_th6=2.640
R_th7=4.32	C_th7=8.500
R_th8=5.12	C_th8=14.200
R_th9=5.19	C_th9=26.000
R_th10=4.75	C_th10=47.800
R_th11=4.66	C_th11=102.000
R_th12=5.87	C_th12=165.000
R_th13=4.08	C_th13=282.000
R_th14=1.04	C_th14=2 410.000

Research on the Impact of Trapped Charges at SiC/SiO₂ Interface on the Short-circuit Performances of SiC MOSFET

doi: 10.3969/j.issn.1001-0548.2019.06.021

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Research on the Impact of Trapped Charges at SiC/SiO₂ Interface on the Short-circuit Performances of SiC MOSFET

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Anhui Provincial Key Laboratory of Power Electronics and Motion Control, Anhui University of Technology Maanshan Anhui 243002

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Research on the Impact of Trapped Charges at SiC/SiO2 Interface on the Short-circuit Performances of SiC MOSFET

doi: 10.3969/j.issn.1001-0548.2019.06.021

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Research on the Impact of Trapped Charges at SiC/SiO2 Interface on the Short-circuit Performances of SiC MOSFET

doi: 10.3969/j.issn.1001-0548.2019.06.021

Anhui Provincial Key Laboratory of Power Electronics and Motion Control, Anhui University of Technology Maanshan Anhui 243002

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Research on the Impact of Trapped Charges at SiC/SiO₂ Interface on the Short-circuit Performances of SiC MOSFET

Research on the Impact of Trapped Charges at SiC/SiO₂ Interface on the Short-circuit Performances of SiC MOSFET