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Article Navigation >  Journal of University of Electronic Science and Technology of China  > 2008  >  37(2): 258-261

JIANG Hong-Bo, HUANG Ying. Verification Methodology Based on FVP[J]. Journal of University of Electronic Science and Technology of China, 2008, 37(2): 258-261.
Citation: JIANG Hong-Bo, HUANG Ying. Verification Methodology Based on FVP[J]. Journal of University of Electronic Science and Technology of China, 2008, 37(2): 258-261.
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Verification Methodology Based on FVP

  • 1.

    Department of Electronics and Information Engineering,Huazhong University of Science and Technology Wuhan 510006;

  • 2.

    School of Computer Science and Engineering,University of Electronic Science and Technology of China Chengdu 610054

  • Received Date: 2007-06-04
  • Rev Recd Date: 2007-12-08
  • Publish Date: 2008-04-15
  • Given the complexity of the functionality of system on chip (SOC), one of the main challenges of current IC design is no more than verification. We implemente a functional virtual prototype (FVP) according to the blueprint of unified verification methodology to solve the synchronization between design and verification in SOC development. The FVP is based on three levels of models:system-level, behavior-level, and register transfer level (RTL). The efficiency of verification can be improved by using FVP as a system-level model.
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  • 1. 

    沈阳化工大学材料科学与工程学院 沈阳 110142

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Verification Methodology Based on FVP

  • 1. Department of Electronics and Information Engineering,Huazhong University of Science and Technology Wuhan 510006;
  • 2. School of Computer Science and Engineering,University of Electronic Science and Technology of China Chengdu 610054
  • Received Date: 2007-06-04
  • Rev Recd Date: 2007-12-08
  • Publish Date: 2008-04-15

Abstract: Given the complexity of the functionality of system on chip (SOC), one of the main challenges of current IC design is no more than verification. We implemente a functional virtual prototype (FVP) according to the blueprint of unified verification methodology to solve the synchronization between design and verification in SOC development. The FVP is based on three levels of models:system-level, behavior-level, and register transfer level (RTL). The efficiency of verification can be improved by using FVP as a system-level model.

JIANG Hong-Bo, HUANG Ying. Verification Methodology Based on FVP[J]. Journal of University of Electronic Science and Technology of China, 2008, 37(2): 258-261.
Citation: JIANG Hong-Bo, HUANG Ying. Verification Methodology Based on FVP[J]. Journal of University of Electronic Science and Technology of China, 2008, 37(2): 258-261.
shu

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