一种中国剩余定理权重预分配方法

MA Shang; WANG Chen-hao; CHEN Hong-yan; HU Jian-hao

Apr. 2016

Article Contents

Article Navigation > Journal of University of Electronic Science and Technology of China > 2016 > 45(2): 161-167

MA Shang, WANG Chen-hao, CHEN Hong-yan, HU Jian-hao. 一种中国剩余定理权重预分配方法[J]. Journal of University of Electronic Science and Technology of China, 2016, 45(2): 161-167.

Citation:

MA Shang, WANG Chen-hao, CHEN Hong-yan, HU Jian-hao. 一种中国剩余定理权重预分配方法[J]. Journal of University of Electronic Science and Technology of China, 2016, 45(2): 161-167.

一种中国剩余定理权重预分配方法

Publish Date: 2016-04-15

Abstract

中国剩余定理(CRT)是获取余数系统(RNS)权重信息的基本理论之一。该文提出了一种CRT的权重预分配方法,通过在一定约束条件下预分配CRT中的权重,使之运算结果保持不变,从而减小获取RNS权重信息或后向转换的复杂度。该方法使得CRT成为本文方法的一个特例,并可通过不同的预分配权重来获得不同的电路实现结构,较CRT方法具有更好的灵活性。此外,结合混合基转换(MRC)还给出了基于这种方法的一个后向转换应用实例。分析结果表明基于本文方法的RNS后向转换具有较好的灵活性,从而可优化RNS后向转换的实现结构。

References

[1]	MA Shang, HU Jian-hao, WANG Chen-hao. A novel modulo 2n-2k-1 adder for residue number system[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2013, 60(11): 2962-2972.
[2]	LIU Y, LAI E M. Design and implementation of an RNS-based 2-D DWT processor[J]. IEEE Trans Consumer Electronics, 2004, 50(1): 376-385.
[3]	PATRONIK P, BEREZOWSKI K, PIESTRAK S J, et al. Fast and energy-efficient constant-coefficient fir filters using residue number system[C]//International Symposium on Low Power Electronics and Design (ISLPED). Fukuoka: IEEE, 2011: 385-390.
[4]	BAJARD J C, DIDIER L S, HILAIRE T. ρ-direct form transposed and residue number systems for filter implementations[C]//IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS). Seoul: IEEE, 2011: 1-4.
[5]	AMIR S M, SAEID S, AZADEH A E Z. Research challenges in next-generation residue number system architectures[C]//7th International Conference on Computer Science & Education (ICCSE). Melbourne, VIC: IEEE, 2012: 1658-1661.
[6]	BANERJI D K, BRZOZOWSKI J A. Sign detection in residue number systems[J]. IEEE Transactions on Computers, 1969, 18(4): 313-320.
[7]	DINA Y, PAVEL S. Universal approaches for overflow and sign detection in residue number system based on {2n-1,2n,2n+1}[C]//The Eighth International Conference on Systems (ICONS). Seville, Spain: ThinkMind, 2013: 77-81.
[8]	MA Shang, HU Jian-hao, YE Yan-long, et al. A scaling scheme for signed RNS integers and its VLSI implementation[J]. Science in China Series F: Information Sciences, 2010, 53(1): 203-212.
[9]	MA S, HU J H, ZHANG L, et al. An efficient RNS parity checker for moduli set {2n-1,,2n+1,22n+1} and its applications[J]. Science in China series F: Information Sciences, 2008, 51(10): 1563-1571.
[10]	SHENOY M A P, KUMARESAN R. Fast base extension using a redundant modulus in RNS[J]. IEEE Transactions on Computers, 1989, 38(2): 292-297.
[11]	WANG Y K. New Chinese remainder theorems[C]//Conference Record of the Thirty-Second Asilomar Conference on Signals, Systems & Computers. Pacific Grove: IEEE, 1998(1): 165-171.
[12]	WANG Y K. Residue-to-binary converters based on new Chinese remainder theorems[J]. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2000, 47(3): 197-205.
[13]	MEEHAN S J, O'NEIL S D, VACCARO J J. An universal input and output RNS converter[J]. IEEE Transactions on Circuits and Systems, 1990, 37(6): 799-803.
[14]	CAO B, CHANG C H,SRIKANTHAN T. An efficient reverse converter for the 4-moduli set based on the new Chinese remainder theorem[J]. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 2003, 50(10): 1296-1303.
[15]	CAO B, SRIKANTHAN T, CHANG C H. Efficient reverse converters for four-moduli sets {2n-1,2n,2n+1,2n+1-1} {2n-1,2n,2n+1,2n-1-1} and [J]. IEEE Proceedings on Computers and Digital Techniques, 2005, 152(5): 687-696.
[16]	WANG W, SWAMY M N S, Ahmad M O, et al. A comprehensive study of three moduli sets for residue arithmetic[C]//IEEE Canadian Conference on Electrical and Computer Engineering. Edmonton: IEEE, 1999(1): 513-518.
[17]	MOHAN P V A. RNS-to-binary converter for a new three-moduli set {2n+1-1,2n,2n-1} [J]. IEEE Transactions on Circuits and Systems, 2007, 54(9): 775-779.
[18]	WEY C L, LIN S Y. VLSI implementation of residue-to-binary converters for digital signal processing[C]//IEEE International Conference on Electro/Information Technology. Chicago: IEEE, 2007: 536-541.
[19]	CAO B, CHANG C H,SRIKANTHAN T. A residue-to-binary converter for a new five-moduli set[J]. IEEE Transactions on Circuits and Systems, 2007, 54(5): 1041-1049.
[20]	WANG W, SWAMY M N S, AHMAD M O, et al. A study of the residue-to-binary converters for the three-moduli sets[J]. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 2003, 50(2): 235-243
[21]	CAO B, SRIKANTHAN T, CHANG C H. Design of a high speed reverse converter for a new 4-moduli set residue number system[C]//Proceedings of the 2003 International Symposium on Circuits and Systems (ISCAS'03). Bangkok: IEEE, 2003(4): 520-523.
[22]	WANG W, SWAMY M N S, AHMAD M O, et al. A high-speed residue-to-binary converter for three-moduli(2k,2k-1,2k-1-1) RNS and a scheme for its VLSI implementation[J]. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2000, 47(12): 1576-1581.
[23]	WANG W, SWAMY M N S, AHMAD M O, et al. A parallel residue-to-binary converter for the moduli set {2m-1,220m+1,221m+1,...,22km+1}[J]. VLSI Design, 2002, 14(2): 183-191.
[24]	HIASAT A A. VLSI implementation of new arithmetic residue to binary decoders[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005, 13(1): 153-158.
[25]	WANG Y, SONG X, ABOULHAMID M, et al. Adder based residue to binary number converters for (2n-1,2n,2n+1) [J]. IEEE Transactions on Signal Processing, 2002, 50(7): 1772-1779.
[26]	GBOLAGADE K A, CHAVES R, Sousa L, et al. An improved RNS reverse converter for the {22n+1-1,2n,2n-1} moduli set[C]//Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS). Paris: IEEE, 2010: 2103-2106.
[27]	WEI L K, NICHOLAS C H V. Design of LUT based RNS reverse converters[C]//IEEE 17th International Symposium on Consumer Electronics (ISCE). Hsinchu: IEEE, 2013: 119-120.
[28]	LIN S H, SHEU M H, LIN J S, et al. Efficient VLSI design for rns reverse converter based on new moduli set (2n-1,2n+1,22n+1)[C]//IEEE Asia Pacific Conference on Circuits and Systems. Singapore: IEEE, 2006: 2020-2023.
[29]	AMIR S M, KEIVAN N, CHITRA D, et al. Efficient reverse converter designs for the new 4-moduli sets {2n-1,2n,2n+1,22n+1-1} and {22-1,22n+1,222n,22n+1} based on new CRTs[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2010, 57(4): 823-835.
[30]	CHEN Shuang-ching, WEI Shu-gang. Weighted-to-residue and residue-to-weighted converters with three-moduli (2n-1,2n,2n+1) signed-digit architectures. Proceedings [C]//2006 IEEE International Symposium on Circuits and Systems(ISCAS). Island of Kos: IEEE, 2006: 3365-3368.
[31]	ANDREAS P, LARS B. Reverse conversion architectures for signed-digit residue number systems[C]//2006 IEEE International Symposium on Circuits and Systems(ISCAS). Island of Kos: IEEE, 2006: 2701-2704.
[32]	JIANG Chang-jun, WEI Shu-gang. Residue-weighted number conversion for moduli set {22n-1,22n+1-1,2n} using signed-digit number[C]//IEEE 10th International New Circuits and Systems Conference (NEWCAS). Montreal: IEEE, 2012: 9-12.

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一种中国剩余定理权重预分配方法

Publish Date: 2016-04-15

Abstract: 中国剩余定理(CRT)是获取余数系统(RNS)权重信息的基本理论之一。该文提出了一种CRT的权重预分配方法,通过在一定约束条件下预分配CRT中的权重,使之运算结果保持不变,从而减小获取RNS权重信息或后向转换的复杂度。该方法使得CRT成为本文方法的一个特例,并可通过不同的预分配权重来获得不同的电路实现结构,较CRT方法具有更好的灵活性。此外,结合混合基转换(MRC)还给出了基于这种方法的一个后向转换应用实例。分析结果表明基于本文方法的RNS后向转换具有较好的灵活性,从而可优化RNS后向转换的实现结构。

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Reference (32)

[1]	MA Shang, HU Jian-hao, WANG Chen-hao. A novel modulo 2n-2k-1 adder for residue number system[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2013, 60(11): 2962-2972.
[2]	LIU Y, LAI E M. Design and implementation of an RNS-based 2-D DWT processor[J]. IEEE Trans Consumer Electronics, 2004, 50(1): 376-385.
[3]	PATRONIK P, BEREZOWSKI K, PIESTRAK S J, et al. Fast and energy-efficient constant-coefficient fir filters using residue number system[C]//International Symposium on Low Power Electronics and Design (ISLPED). Fukuoka: IEEE, 2011: 385-390.
[4]	BAJARD J C, DIDIER L S, HILAIRE T. ρ-direct form transposed and residue number systems for filter implementations[C]//IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS). Seoul: IEEE, 2011: 1-4.
[5]	AMIR S M, SAEID S, AZADEH A E Z. Research challenges in next-generation residue number system architectures[C]//7th International Conference on Computer Science & Education (ICCSE). Melbourne, VIC: IEEE, 2012: 1658-1661.
[6]	BANERJI D K, BRZOZOWSKI J A. Sign detection in residue number systems[J]. IEEE Transactions on Computers, 1969, 18(4): 313-320.
[7]	DINA Y, PAVEL S. Universal approaches for overflow and sign detection in residue number system based on {2n-1,2n,2n+1}[C]//The Eighth International Conference on Systems (ICONS). Seville, Spain: ThinkMind, 2013: 77-81.
[8]	MA Shang, HU Jian-hao, YE Yan-long, et al. A scaling scheme for signed RNS integers and its VLSI implementation[J]. Science in China Series F: Information Sciences, 2010, 53(1): 203-212.
[9]	MA S, HU J H, ZHANG L, et al. An efficient RNS parity checker for moduli set {2n-1,,2n+1,22n+1} and its applications[J]. Science in China series F: Information Sciences, 2008, 51(10): 1563-1571.
[10]	SHENOY M A P, KUMARESAN R. Fast base extension using a redundant modulus in RNS[J]. IEEE Transactions on Computers, 1989, 38(2): 292-297.
[11]	WANG Y K. New Chinese remainder theorems[C]//Conference Record of the Thirty-Second Asilomar Conference on Signals, Systems & Computers. Pacific Grove: IEEE, 1998(1): 165-171.
[12]	WANG Y K. Residue-to-binary converters based on new Chinese remainder theorems[J]. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2000, 47(3): 197-205.
[13]	MEEHAN S J, O'NEIL S D, VACCARO J J. An universal input and output RNS converter[J]. IEEE Transactions on Circuits and Systems, 1990, 37(6): 799-803.
[14]	CAO B, CHANG C H,SRIKANTHAN T. An efficient reverse converter for the 4-moduli set based on the new Chinese remainder theorem[J]. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 2003, 50(10): 1296-1303.
[15]	CAO B, SRIKANTHAN T, CHANG C H. Efficient reverse converters for four-moduli sets {2n-1,2n,2n+1,2n+1-1} {2n-1,2n,2n+1,2n-1-1} and [J]. IEEE Proceedings on Computers and Digital Techniques, 2005, 152(5): 687-696.
[16]	WANG W, SWAMY M N S, Ahmad M O, et al. A comprehensive study of three moduli sets for residue arithmetic[C]//IEEE Canadian Conference on Electrical and Computer Engineering. Edmonton: IEEE, 1999(1): 513-518.
[17]	MOHAN P V A. RNS-to-binary converter for a new three-moduli set {2n+1-1,2n,2n-1} [J]. IEEE Transactions on Circuits and Systems, 2007, 54(9): 775-779.
[18]	WEY C L, LIN S Y. VLSI implementation of residue-to-binary converters for digital signal processing[C]//IEEE International Conference on Electro/Information Technology. Chicago: IEEE, 2007: 536-541.
[19]	CAO B, CHANG C H,SRIKANTHAN T. A residue-to-binary converter for a new five-moduli set[J]. IEEE Transactions on Circuits and Systems, 2007, 54(5): 1041-1049.
[20]	WANG W, SWAMY M N S, AHMAD M O, et al. A study of the residue-to-binary converters for the three-moduli sets[J]. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 2003, 50(2): 235-243
[21]	CAO B, SRIKANTHAN T, CHANG C H. Design of a high speed reverse converter for a new 4-moduli set residue number system[C]//Proceedings of the 2003 International Symposium on Circuits and Systems (ISCAS'03). Bangkok: IEEE, 2003(4): 520-523.
[22]	WANG W, SWAMY M N S, AHMAD M O, et al. A high-speed residue-to-binary converter for three-moduli(2k,2k-1,2k-1-1) RNS and a scheme for its VLSI implementation[J]. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2000, 47(12): 1576-1581.
[23]	WANG W, SWAMY M N S, AHMAD M O, et al. A parallel residue-to-binary converter for the moduli set {2m-1,220m+1,221m+1,...,22km+1}[J]. VLSI Design, 2002, 14(2): 183-191.
[24]	HIASAT A A. VLSI implementation of new arithmetic residue to binary decoders[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005, 13(1): 153-158.
[25]	WANG Y, SONG X, ABOULHAMID M, et al. Adder based residue to binary number converters for (2n-1,2n,2n+1) [J]. IEEE Transactions on Signal Processing, 2002, 50(7): 1772-1779.
[26]	GBOLAGADE K A, CHAVES R, Sousa L, et al. An improved RNS reverse converter for the {22n+1-1,2n,2n-1} moduli set[C]//Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS). Paris: IEEE, 2010: 2103-2106.
[27]	WEI L K, NICHOLAS C H V. Design of LUT based RNS reverse converters[C]//IEEE 17th International Symposium on Consumer Electronics (ISCE). Hsinchu: IEEE, 2013: 119-120.
[28]	LIN S H, SHEU M H, LIN J S, et al. Efficient VLSI design for rns reverse converter based on new moduli set (2n-1,2n+1,22n+1)[C]//IEEE Asia Pacific Conference on Circuits and Systems. Singapore: IEEE, 2006: 2020-2023.
[29]	AMIR S M, KEIVAN N, CHITRA D, et al. Efficient reverse converter designs for the new 4-moduli sets {2n-1,2n,2n+1,22n+1-1} and {22-1,22n+1,222n,22n+1} based on new CRTs[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2010, 57(4): 823-835.
[30]	CHEN Shuang-ching, WEI Shu-gang. Weighted-to-residue and residue-to-weighted converters with three-moduli (2n-1,2n,2n+1) signed-digit architectures. Proceedings [C]//2006 IEEE International Symposium on Circuits and Systems(ISCAS). Island of Kos: IEEE, 2006: 3365-3368.
[31]	ANDREAS P, LARS B. Reverse conversion architectures for signed-digit residue number systems[C]//2006 IEEE International Symposium on Circuits and Systems(ISCAS). Island of Kos: IEEE, 2006: 2701-2704.
[32]	JIANG Chang-jun, WEI Shu-gang. Residue-weighted number conversion for moduli set {22n-1,22n+1-1,2n} using signed-digit number[C]//IEEE 10th International New Circuits and Systems Conference (NEWCAS). Montreal: IEEE, 2012: 9-12.

一种中国剩余定理权重预分配方法

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