Volume 36 Issue 4
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Article Navigation >  Journal of University of Electronic Science and Technology of China  > 2007  >  36(4): 751-754

YANG De-cai, CHEN Guang-ju, XIE Yong-le. A Built-in Self-Test Scheme for Carry Save Array Multiplier[J]. Journal of University of Electronic Science and Technology of China, 2007, 36(4): 751-754.
Citation: YANG De-cai, CHEN Guang-ju, XIE Yong-le. A Built-in Self-Test Scheme for Carry Save Array Multiplier[J]. Journal of University of Electronic Science and Technology of China, 2007, 36(4): 751-754.
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A Built-in Self-Test Scheme for Carry Save Array Multiplier

  • 1.

    School of Automation Engineering,University of Electronic Science and Technology of China Chengdu 610054

  • Received Date: 2006-05-15
  • Publish Date: 2006-08-15
  • A built-in self-test scheme is presented for a carry save array multiplier in which an accumulator is designed as a test pattern generator and a response compactor. A modified deterministic test sequence is deduced. Analysis and Experiment results show that all the non-redundant stuck-at faults can be covered. As in current Very Large Scale Integration (VLSI) circuits accumulators commonly exist with multipliers, this scheme can lead to minimum hardware overhead and performance degradation by reusing available accumulators to generate test vectors and compact test responses. Moreover, this scheme can achieve the goal of short test sequences and high fault coverage.
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  • 1. 

    沈阳化工大学材料科学与工程学院 沈阳 110142

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A Built-in Self-Test Scheme for Carry Save Array Multiplier

  • 1. School of Automation Engineering,University of Electronic Science and Technology of China Chengdu 610054
  • Received Date: 2006-05-15
  • Publish Date: 2006-08-15

Abstract: A built-in self-test scheme is presented for a carry save array multiplier in which an accumulator is designed as a test pattern generator and a response compactor. A modified deterministic test sequence is deduced. Analysis and Experiment results show that all the non-redundant stuck-at faults can be covered. As in current Very Large Scale Integration (VLSI) circuits accumulators commonly exist with multipliers, this scheme can lead to minimum hardware overhead and performance degradation by reusing available accumulators to generate test vectors and compact test responses. Moreover, this scheme can achieve the goal of short test sequences and high fault coverage.

YANG De-cai, CHEN Guang-ju, XIE Yong-le. A Built-in Self-Test Scheme for Carry Save Array Multiplier[J]. Journal of University of Electronic Science and Technology of China, 2007, 36(4): 751-754.
Citation: YANG De-cai, CHEN Guang-ju, XIE Yong-le. A Built-in Self-Test Scheme for Carry Save Array Multiplier[J]. Journal of University of Electronic Science and Technology of China, 2007, 36(4): 751-754.
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