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Article Navigation >  Journal of University of Electronic Science and Technology of China  > 2003  >  32(5): 574-577

Zhou Liang. A New Iterative Implementation and Architecture for LOG-MAP Algorithm[J]. Journal of University of Electronic Science and Technology of China, 2003, 32(5): 574-577.
Citation: Zhou Liang. A New Iterative Implementation and Architecture for LOG-MAP Algorithm[J]. Journal of University of Electronic Science and Technology of China, 2003, 32(5): 574-577.
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A New Iterative Implementation and Architecture for LOG-MAP Algorithm

  • 1.

    National Key Laboratory of Communication,UEST of China Chengdu 610054

  • Received Date: 2003-09-01
  • Publish Date: 2003-10-15
  • This paper analyzes the parallel mechanism of logarithmic maximum a posteriori algorithm and presents a modified iterative procedure by the use of the possibility of receiving the full N-symbols frame and the symmtry being inherent in the forward-backward iteration. The procedure achieves a double decoding speed faster than that of the conventional one without the increase of RAM cost because the number of iterations is limited to a half of the code-length N. Also according to the modified algorithm this paper proposes a hardware scheme characterized by a two-busses architecture suitable for implementing with FPGA.
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    沈阳化工大学材料科学与工程学院 沈阳 110142

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A New Iterative Implementation and Architecture for LOG-MAP Algorithm

  • 1. National Key Laboratory of Communication,UEST of China Chengdu 610054
  • Received Date: 2003-09-01
  • Publish Date: 2003-10-15

Abstract: This paper analyzes the parallel mechanism of logarithmic maximum a posteriori algorithm and presents a modified iterative procedure by the use of the possibility of receiving the full N-symbols frame and the symmtry being inherent in the forward-backward iteration. The procedure achieves a double decoding speed faster than that of the conventional one without the increase of RAM cost because the number of iterations is limited to a half of the code-length N. Also according to the modified algorithm this paper proposes a hardware scheme characterized by a two-busses architecture suitable for implementing with FPGA.

Zhou Liang. A New Iterative Implementation and Architecture for LOG-MAP Algorithm[J]. Journal of University of Electronic Science and Technology of China, 2003, 32(5): 574-577.
Citation: Zhou Liang. A New Iterative Implementation and Architecture for LOG-MAP Algorithm[J]. Journal of University of Electronic Science and Technology of China, 2003, 32(5): 574-577.
shu

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