Abstract: To deal with the slow operation speed in the existing single-precision floating-point multiplier, a fast Karatsuba-based single-precision floating-point multiplier which combines the advantages of Karatsuba algorithm with the Vedic algorithm is designed in this paper. The fast Karatsuba-based multiplier decreases the multiplication-operation times of the conventional single-precision floating-point multiplier by splitting the multiplication of 24-bit mantissa into that of fewer mantissa. An improved multiplication architecture composed of the 3-bit and 4-bit mantissa is constructed and further optimized by employing the Vedic algorithm. The 3-bit and 4-bit multipliers are respectively achieved by the corresponding adders with low complexity and fast speed, leading to faster processing speed. The results of simulation and FPGA verification imply that the designed single-precision floating-point multiplier achieves approximately 5 times and 2 times higher performance in the maximum operating clock frequency, comparing to the conventional Karatsuba-based and the Vedic-based single-precision floating-point multiplier, respectively.