10 kV SiC LBD-MOSFET结构设计与特性研究

Design and Characteristics of a Novel 10 kV SiC MOSFET Embedding Low Barrier Diode

  • 摘要: 针对SiC MOSFET体二极管双极退化效应,该文提出了一种集成低势垒二极管的10 kV SiC MOSFET器件新结构(LBD-MOSFET)。该结构通过在一侧基区上方注入N阱,降低了漏源间的电子势垒,从而在元胞中形成一个低势垒二极管(LBD)。当LBD-MOSFET在第三象限工作时,低的电子势垒使LBD以更低的源漏电压开启,有效避免了体二极管开通所导致的双极退化效应。二维数值分析结果表明,SiC LBD-MOSFET的击穿电压达13.5 kV,第三象限开启电压仅为1.3 V,相比传统结构降低48%,可有效降低器件第三象限导通损耗。同时,由于LBD-MOSFET具有较小的栅漏交叠面积,其栅漏电容仅为1.0 pF/cm2,器件的高频优值为194 mΩ·pF,性能相比传统结构分别提升了81%和76%。因此,LBD-MOSFET适用于高频高可靠性电力电子系统。

     

    Abstract: In this paper, a novel 10 kV SiC MOSFET embedding low barrier diode (LBD-MOSFET) is proposed and researched to solve the bipolar degradation effect in SiC MOSFET. The low barrier diode (LBD) in the cell is formed by introducing an N_well above the P_base region on one side, which reduces the electron barrier between the drain and the source. When the LBD-MOSFET works in the third quadrant, the low electronic barrier makes the LBD turn on with a lower source-drain voltage, thus effectively avoiding the bipolar degradation effect caused by the turn-on of the body diode. 2D numerical analysis results show that the breakdown voltage of the SiC LBD-MOSFET reaches 13.5 kV. In the third quadrant, the turn-on voltage is only 1.3 V, which is 48% lower than the traditional structure and effectively reduces the conduction loss of the device. At the same time, since the gate-drain overlap area of the LBD-MOSFET is reduced compared to the traditional MOSFET, the Cgd is only 1.0 pF/cm2 and the high-frequency merit value of the device is 194 mΩ·pF, which are reduced by 81% and 76% compared with the traditional MOSFET, respectively. Therefore, the LBD-MOSFET is suitable for high-frequency and high-reliability power electronic systems.

     

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