SoC软硬件协同技术的FPGA芯片测试新方法

李平; 廖永波; 阮爱武; 李威; 李文昌

doi:10.3969/j.issn.1001-0548.2009.05.034

SoC软硬件协同技术的FPGA芯片测试新方法

电子科技大学电子薄膜与集成器件国家重点实验室成都 610054

基金项目:

部级预研基金

详细信息

作者简介:
李平(1957-)，男，教授，博士生导师，主要从事FDGA芯片设计、红外读出电路芯片设计等方面的研究

中图分类号: TP206+.1
计量
- 文章访问数: 4672
- HTML全文浏览量: 134
- PDF下载量: 164
出版历程
- 收稿日期: 2009-05-25
- 刊出日期: 2009-10-14

Novel Approach to Test Field Programmable Gate Array Based on SoC HW/SW Co-Verification Technology

State Key Laboratory of Electronic Thin Films and Integrated Devices,University of Electronic Science and Technology of China Chengdu 610054

摘要

摘要: 针对传统的基于纯硬件平台的FPGA芯片测试方法所存在的种种问题,提出并验证了一种基于软硬件协同技术的FPGA芯片测试方法。该方法引入了软件的灵活性与可观测性等软件技术优势,具有存储深度大、可测I/O管脚数目多、自动完成配置下载(不需人工干预)和自动定位FPGA中的错误等优点,提高了FPGA的测试速度和可靠性,并降低了测试成本,与传统的自动测试仪(ATE)相比有较高的性价比。采用软硬件协同方式针对Xilinx 4010的I/O单元进行了测试,实现了对FPGA芯片的自动反复配置、测试和错误定位。
- 配置 /
- 可编辑门阵列 /
- 软硬件协同 /
- 片上系统 /
- 测试
Abstract: Traditional field programmable gate array (FPGA) test schemes confront many problems, such as memory depth not large enough to meet requirement of configuration of many times, I/O pin counts usually less than needed, manual configuration generation and download, no position of fault sites, etc. A new approach to test FPGA based on SoC HW/SW co-verification technology is proposed and verified in the paper. This test scheme has taken advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware. As a result, efficiency and reliability of the test can be enhanced without manual work. In the experiment, the proposed test approach has been applied to a Xilinx 4010 FPGA to implement automatic configuration, test as well as location of fault sites.
- configuration /
- FPGA /
- HW/SW co-verification /
- system on chip /
- test