Abstract: Some useful parallel processing algorithms for the demodulator in a high rate data communication system are presented, including parallel FIR filter, parallel symbol synchronization, and parallel carrier recovery. After analyzing the characteristics of frequency domain parallel FIR filtering, a time domain parallel processing scheme is proposed， which can implement a demodulator for 600 Mb/s digital modulation signal with quite low hardware complexity. The paper proposes a scheme of high precise symbol synchronization loop based on parallel processing and multi-phase filter, which can remarkably improve the synchronization accuracy without sampling rate increasing and almost with no extra complexity. Finally, some testing results of a prototype of high rate data communication system based on the above algorithms are given.