Abstract: A lower power digital correction model for comparator offset and noise tolerance of successive approximation register (SAR) analog-to-digital converter (ADC) is presented. A fine comparator with smaller offset and noise has penalty of higher power and lower speed. This model involves a faster coarse comparator with less power in the first (n-m-1) cycles to relax those penalties. The errors of the coarse comparator are tolerated by the fine comparator through the redundant comparison cycle and the capacitor at (m+2) cycle. This model is able to tolerate noise and offset errors up to ±2m least significant bit (LSB). A prototype of 10 bit 100 MS/s SAR ADC with this model is simulated in a 0.13μm CMOS technology. The post-simulation results of the prototype layout witnessed an effective number of bits (ENOB) of 9.27 bit are achieved at 100 MS/s with a power consumption of 2.01mW under 1.2V supply, resulting in a figure of merit (FoM) of 33fJ/conv.