Abstract: Increasingly complicated very large scale integration (VLSI) design and system-on-chip (SoC) makes Field Programmable Gate Arrays (FPGA)-based emulation necessary. As a design is downloaded into a FPGA-based emulator, invisible internal nodes of the design pose a challenge for design debugging. To address the issue, a RTL-level runtime debugging system is proposed. The user can not only select sample signals, triggering signals and statements in RTL codes, but can change triggering mode or sample window runtime as well. The proposed debugging system supports three debugging modes including embedded logic analyzer (ELA) mode, scan mode and snapshot mode. All debugging modes use a unified external interface in order to make the debugging system suitable for both Altera and Xilinx FPGAs. Experiment results show that the ELA mode consumes nearly the same resources while the scan mode and snapshot mode consumes fewer resources, compared with SignalTap and ChipScope.