Abstract: There are quite long interconnection lines between the nodes of a network-on-chip (NoC) based on the globally asynchronous locally synchronous (GALS) structure. It is difficult to match the delay requirement for the communication with the asynchronous ways. In this paper, we propose a build-in self-test (BIST) method to solve the problem of interconnection delay fault across different clock domains. The test circuit and the module of automatic test pattern generation (ATPG) are designed and simulated. The circuit with FPGA is realized to verify the function and performance of the test circuit. The results of simulation and hardware verification indicate that test circuit and the module of ATPG can carry out the function of interconnection delay fault diagnosis of NoC, and the proposed method of interconnection delay fault diagnosis can detect the delay fault existed in the interconnection line rapidly and accurately.