Abstract: With the rapid development of microelectronics manufacture process, the reliability of flash memory has become more and more significant especially beyond 65 nm technology node. One of the most critical reliability issues is that the erase speed of flash memory chip degrades obviously with the increase of erase cycle. In this paper, the erasure degradation characteristics of flash cell were carefully reviewed. The generation mechanism of the tunneling oxide defect and its effects on device performance degradation are also well discussed. The optimization schemes are then proposed in this paper, including low stress program/erase scheme with staircase pulse and disturb-immune array bias condition for the unselected Sectors. A 128 Mb flash memory chip is developed based on SMIC 65 nm NOR flash technology to verify the optimization schemes. The testing results show that the Sector erase time of the optimized chip after 105 program/erase cycles is 104.9 ms, which is obviously improved compared with that of the conventional flash chip (more than 200 ms).