组合电路门时滞故障的可测性分析
Analysis of Gate Delay Fault's Testability in Combinational Circuits
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摘要: 根据时滞故障测试的特点,定义了一种门时滞故障的可测性测度(即上升沿和下降沿门时滞故障的可控制性和可观测性),并提出了相应的计算方法,为基于门时滞故障的电路可测性论计提供了理论依据。Abstract: According to the feature of the testing for gate delay faults, the testability measures of the gate delay faults are defined (the controllability and the observability of the gate delay faults in the rising or falling transition), and the method of computing these two measures are presented, which provides the quantitative criteria of design for testability of the gate delay faults.