Pipeline Design of LDPC Decoder Based on Frame-Interleaving

The decoder of low density parity check code (LDPC) generally adopts an iterative algorithm based on node confidence update, which can be implemented in parallel and has very high throughput. In this paper, we propose a frame-interleaving decoding structure with high hardware utilization efficiency (HUE) features and develop a dynamic planning method for node reordering within layers, which can solve the memory access conflict problems. Compared with the existing structures, the proposed structure shows more efficiency with respect to hardware utilization.