Architecture, VLSI Implementation of Inter Compensator for AVS HDTV Application

An efficient inter predictive pixel compensator for audio video coding standard (AVS) is presented. It generates one predictive pixel result per cycle, uses dual-port memory to reduce data latency. 3-stage pipeline architecture is used to calculate compensation pixel for increasing frequency, 3-stage reusable filters are used to calculate the 1/4 predictive pixel for saving circuit cost. Simulation shows that the module implemented can achieve AVS HD real-time decoding.