Optimization Techniques of Static Power Dissipation in Chip with Dynamical Threshold

A novel dynamic threshold static power optimization algorithm is presented. After accounting the relaxation margins of gate level nodes, the maximum margin in circuits and characteristics in adjacent gates are analyzed with static timing, the key and non-key nodes are then divided, their thresholds are adjusted within stages, and the efficient power optimization of CMOS circuits is finally implemented. Compared with existing algorithms, experimental results with ISCA85 benchmark circuits show that processing time of the algorithm can be reduced 95% at lest without reducing the optimization efficiency of static power.