Novel Approach to Test Field Programmable Gate Array Based on SoC HW/SW Co-Verification Technology

Traditional field programmable gate array (FPGA) test schemes confront many problems, such as memory depth not large enough to meet requirement of configuration of many times, I/O pin counts usually less than needed, manual configuration generation and download, no position of fault sites, etc. A new approach to test FPGA based on SoC HW/SW co-verification technology is proposed and verified in the paper. This test scheme has taken advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware. As a result, efficiency and reliability of the test can be enhanced without manual work. In the experiment, the proposed test approach has been applied to a Xilinx 4010 FPGA to implement automatic configuration, test as well as location of fault sites.