Gate Tunneling Current Predicting Model for Scaled Devices

With the scaling of MOS devices, gate tunneling current increases significantly due to thinner gate oxides, and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents. In this paper, a novel gate tunneling current predicting model using integral means is presented for ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness. To analyze quantitatively the behaviors of scaled MOS devices in the effects of gate tunneling current and predict the trends, the characteristics of MOS devices are studied in detail using H-Simulation program with integrated circuit emphasis (HSPICE) simulator. The simulation results in BSIM 4 model well agree with the model proposed. The theory and experiment data are contributed to the VLSI circuit design in the future.