Design of Constant-Gain Digitally Controlled Oscillator

The gain of the driven-adjustable digitally controlled oscillator (DCO) varies largely in the output frequency range. To solve the problem, a circuit design method is presented to keep the DCO gain invariant in time-domain. To verify the proposed design method, a digitally controlled phase-locked loop (DCPLL) with the DCO is implemented by SMIC 0.18 μm logic 1P6M CMOS technology. The area of the DCO is 0.025 mm2. The measured results show that the frequency range of the DCO is from 76 MHz to 208 MHz. When the frequency of the DCO is 208 MHz, the measured peak-to-peak jitter and cycle jitter of the corresponding four-divided clock are 110 ps and 14.82 ps, respectively. The corresponding power of the DCO is 1.512 mW.