Review on Productivity Improvement of SoC Hardware Verification

As system on chip (SoC) design complexity explodes, the gap between chip design and verification has been widened. How to improve verification productivity represents a great challenge to the IC industry. Recent efforts in addressing this challenge are reviewed and then a new verification paradigm, verification-while-designing, is proposed. This methodology combines hierarchical design and recursive verification, aiming at releasing the verification challenge. The fundamental points enabling the methodology are also outlined.