Design and Implementation of Distributed Systolic Array Processor for WLAN MIMO-OFDM Systems

To reduce the delay of QR-decomposition in WLAN (wireless local area network) MIMO-OFDM (multiple input multiple output and orthogonal frequency division multiplexing) systems, a distributed systolic array processor (DSAP) is proposed. The structure uses the coordinate rotation digital computer (CORDIC) in the boundary and internal cells of systolic array, and distributes the QR-decomposition of different sub-carriers into the different stages of the pipelining operation of CORDIC in systolic array. Compared with serial systolic array processor (SSAP), the clock periods can be put to great use in the DSAP, and the delay is reduced by 92% with the same complexity. In SMIC 0.18μm CMOS technology, a 2 ×2 analog-digital mixed MIMO-OFDM chip with DSAP has been implemented, and the test results show that it can reduce the delay of data processing effectively.