A Single Event Multiple Upset Tolerant Hardening Latch with Triple Interlock

In nanometer process, a single event induced multiple upset cannot be ignored. A novel triple interlock hardening latch is proposed for tolerating single event multiple upset. The proposed latch employs code word state preserving (CWSP) cell which has the filtering function to compose triple interlock. At the end of latch, the CWSP cell is also exploited to tolerate single event multiple upset. The simulation results of HSPICE suggest that compared to triple modular redundancy (TMR) latch and DNCS-SEU latch, the power delay product of the proposed latch is reduced by 58.93% and 41.56% respectively. Meanwhile, the proposed latch has less sensitiveness to process variations.