Research on the Impact of Trapped Charges at SiC/SiO₂ Interface on the Short-circuit Performances of SiC MOSFET

The decrease in the trapped charges at SiC/SiO₂ interface is helpful to lower the on-state resistance and switching loss of SiC MOSFET, however, the lift of channel current brings higher current stress to SiC MOSFET during short-circuit case. On the basis of the traditional equivalent circuit model for SiC MOSFET, a short-circuit failure model of SiC MOSFET has been developed. The model introduces the leakage current across the PN junction between N-drift region and P base region of SiC MOSFET, and employs an advance carrier mobility model with the trapped charges at the SiC/SiO₂ interface. By the developed failure model, the influence brought by the interface trapped charges on the short-circuit performances has been exploited, and the result shows that the reduction of interface trapped charge shortens the time of SiC MOSFET withstanding short-circuit stress. Further, the mechanism of interface trapped charges affecting the short-circuit withstanding time has been discussed by separating the leakage current components from the failure current.