Efficient Design of Wideband Digital Receiver on FPGA

A method to design wideband digital receiver on filed programmable gates array (FPGA) is proposed in this paper. The coordinate rotation digital computer (CORDIC) algorithm is employed to generate real time numerically controlled oscillator (NCO) data. Double frequency conversion, quarter decimation and polyphase filters further enhance the system performance. The proposed receiver is more flexible, less computation and less resource consumption. Design example and simulation results are shown to testify the validities and feasibilities.