A Pipeline Architecture for High Speed Square Root

The technique about how to use pipeline architecture to design high speed square root hardware is illustrated through the process of designing a square root circuit of 32 bits integer. By taking into account of the capacity of FPGA, the resources consumed by the square root hardware is analyzed. The new method to solve the extraction of a root is presented, which can deal with the 32 bits sampled data within a clock period. This method is of high precision, fast speed, easily realization. Compared with the conventional one, the division operations are avoided completely in the new algorithm. Thus, the speed of radication has increased by one time.