Verification Methodology Based on FVP

Given the complexity of the functionality of system on chip (SOC), one of the main challenges of current IC design is no more than verification. We implemente a functional virtual prototype (FVP) according to the blueprint of unified verification methodology to solve the synchronization between design and verification in SOC development. The FVP is based on three levels of models:system-level, behavior-level, and register transfer level (RTL). The efficiency of verification can be improved by using FVP as a system-level model.