CHEN Jun, SANG Nan, XIONG Guang-ze. Design and Implementation of a Fault-Tolerance Real-Time Computer Architecture[J]. Journal of University of Electronic Science and Technology of China, 2007, 36(5): 846-849.
Citation: CHEN Jun, SANG Nan, XIONG Guang-ze. Design and Implementation of a Fault-Tolerance Real-Time Computer Architecture[J]. Journal of University of Electronic Science and Technology of China, 2007, 36(5): 846-849.

Design and Implementation of a Fault-Tolerance Real-Time Computer Architecture

  • Based on fault-tolerance technique and multi-processors system, a fault-tolerance real-time embedded dual system solusion is put forward in this paper. The proposed solusion is based upon the loosely coupled multiprocessors architecture. this architecture seamlessly. integrates the fault-tolerance design techniques of hardware level, operating system level, and application level The system reliability is analyzed by the Markov state diagram The results show that the design scheme can enhance the system reliability remarkably.
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