A Speed Analysis Methodology for Pipelined A/D Converters

A speed analysis methodology for a switched-capacitor pipelined A/D converter is presented. The conversion speed of a pipelined A/D converter is determined by the settling speed of the switched-capacitor feedback amplifier in the conversion stage. According to the principle of the pipelined architecture, the formula of the equivalent input step voltage seen at the input nodes of the op-amp is obtained. Then by dividing the settling phase into the large-signal and small-signal mode and using different op-amp model in the different mode, the expression which shows the relationship between the settling time and circuit parameters such as the value of sampling capacitors or op-amp specifications is obtained. Finally, the proposed methodology and the obtained expression are verified by the MATLAB simulation on a 10-bit pipelined ADC.