FANG Han, HUANG Quan-ping, ZHOU Rong-zheng, HONG Zhi-liang. VLSI Implement of JPEG2000 Arithmetic Decoder[J]. Journal of University of Electronic Science and Technology of China, 2006, 35(6): 920-923.
Citation:
FANG Han, HUANG Quan-ping, ZHOU Rong-zheng, HONG Zhi-liang. VLSI Implement of JPEG2000 Arithmetic Decoder[J]. Journal of University of Electronic Science and Technology of China, 2006, 35(6): 920-923.
FANG Han, HUANG Quan-ping, ZHOU Rong-zheng, HONG Zhi-liang. VLSI Implement of JPEG2000 Arithmetic Decoder[J]. Journal of University of Electronic Science and Technology of China, 2006, 35(6): 920-923.
Citation:
FANG Han, HUANG Quan-ping, ZHOU Rong-zheng, HONG Zhi-liang. VLSI Implement of JPEG2000 Arithmetic Decoder[J]. Journal of University of Electronic Science and Technology of China, 2006, 35(6): 920-923.
This paper introduces JPEG2000 encode and decode flow, and also the principle of JPEG2000 arithmetic coding. Traditional arithmetic decoder is very slow that may be the bottleneck of the JPEG2000 system. To solve this problem, a pipeline arithmetic decoder is present here, together with the hardware chart. The arithmetic decoder is verified with FPGA and is implemented in TSMC 0.25 μm technology.
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