High Efficient and Real-Time Realization of Decimation Filter Based on FPGA

This paper briefly talks about the principle of distributed arithmetic algorithm and its application to the multiply-accumulate before puts forward a improved distributed arithmetic algorithm which suits the look up table structure of filed programmable gate array well. Simulated and tested results on real device shows that high efficient and real-time decimation filter with some invariable pipeline delay can be achieved through this improved algorithm. The fabricated decimation filters are used in real digital receiver.