Analysis and Design of Monolithic DC/DC Converters

The challenges and tradeoffs in designing a monolithic DC/DC converter including planner inductor using 0.35 μm CMOS technology on silicon substrate are described by analyzing the power dissipation of the converters. The efficiency of the converter is optimized. The physical design and geometric parameters optimization of the desired planar inductor are given. A double-layer spiral inductor with quality factor of 2.3, area of 0.38 square millimeters, inductance of 35 nH are obtained. From the simulated results, a steady Buck converter with the efficiency of 62% is achieved.