A New Fault Model for Testing Signal Integrity in SoCs

Based on the in-depth research of the property of crosstalk fault, we presented a more efficiency Half Transition (HT) model to detecting signal integrity fault in System-on-Chip (SoC) interconnects between IP cores. In comparison with Maximal Aggressor Fault (MAF) model and Multiple Transition (MT) model, this HT model can achieve 100% faults coverage and need less test pattern. The result of theoretic analyses shows the HT model's excellence in comparison with MAF model in fault coverage and with to MT model in test pattern's efficiency.