A FPGA-Base High-Speed Image Pre-Processing System Design

A single-chip Field Programmable Gate Array(FPGA) Image pre-processing system is introduced. This system is used to complete a series of real-time, multi-task and high-speed image processing tasks, including improving image signal-to-noise ratios, compressing data volume, stokes parameters observation, instrument control and observation mode control, etc. As an on-board system, the reliability of the system is very important, so the core logic modules are redundant. Moreover, Built-in Testing(BIT) module and EDAC(Error Detection And Correction) module are also placed in FPGA. System clock was 40 MHz, and its images processing ratio attained to 100 MHz.