Realization of High-Speed FFT by FPGA

In this paper, the basic principle of decimation-in-frequnency radix-2 FFT algorithm is briefly presented. Then, the design and realization methods of hardware system with FPGA are thoroughly discussed, with which it is easy to implement the FFT algorithm of large points-4 096 points. The FFT-speed of many groups of large points is accelerated greatly through ping-pong-ram. Finally, this hardware system is turned out to be feasible and accurate through the FFT algorithm experiment. Furthermore, the real-time imaging procession of airborne SAR can be accomplished successfully by this hardware system.