Fast Power Grid Analysis Using Multigrid Method

Power grid analysis is an important issue for circuit design and verification. With the increasing number of transistors on a chip, the size of the power networks has grown so large as to make the verification task very challenging. Fast and memory-saving power analysis algorithms are needed. In this paper, we present a fast power grid analyzer using multigrid technique, which speed up the convergence of sparse iterative solver. we proposed a simple and intuitive restriction and interpolation scheme, which is based on the electric distance between the nodes in the power grid network. The convergence can be controlled by a user specified threshold parameter and pre/post smoothing iterations. Experimental results show the efficiency of the new method.