HAN Liang, LI Ying, ZHANG Xin, CHEN Jie. Data Path Design in High Performance Reconfigurable DSP Processor[J]. Journal of University of Electronic Science and Technology of China, 2005, 34(2): 194-197.
Citation: HAN Liang, LI Ying, ZHANG Xin, CHEN Jie. Data Path Design in High Performance Reconfigurable DSP Processor[J]. Journal of University of Electronic Science and Technology of China, 2005, 34(2): 194-197.
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Data Path Design in High Performance Reconfigurable DSP Processor

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  • In this paper, the data path of a high performance reconfigurable DSP processor is introduced. Based on its several 16-bit fixed-point computational units with powerful functions, the data path forms a 16-bit high-speed signal processing platform. By SIMD means, it can flexibly support computations of multi-dimension vector. By the way of reconfiguration, it can efficiently support 32-bit data processing.
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